Select Publications

by Dr Hui Wu

Journal articles

Zheng W; Wu H, 2014, 'WCET-aware dynamic instruction cache locking', ACM SIGPLAN Notices, vol. 49, no. 5, pp. 53 - 62, http://dx.doi.org/10.1145/2597809.2597820

Alghamdi WY; Wu H; Fei J; Kanhere SS, 2014, 'Randomised multipath routing for secure data collection', IEEE ISSNIP 2014 - 2014 IEEE 9th International Conference on Intelligent Sensors, Sensor Networks and Information Processing, Conference Proceedings, http://dx.doi.org/10.1109/ISSNIP.2014.6827598

Zhang X; Wu H; Xue J, 2012, 'Instruction scheduling with k-successor tree for clustered VLIW processors', Design Automation for Embedded Systems, pp. 1 - 20, http://dx.doi.org/10.1007/s10617-012-9103-0

Di P; Wu H; Xue J; Wang F; Yang C, 2012, 'Parallelizing SOR for GPGPUs using alternate loop tiling', Parallel Computing, vol. 38, no. 6-7, pp. 310 - 328, http://dx.doi.org/10.1016/j.parco.2012.03.004

Wu H; Chin WN; Jaffar J, 2002, 'An Effcient Distribution Dealine Avoidance Algorithm for the AND Model', IEEE Transactions on Software Engineering, vol. 28, pp. 18 - 29

Conference Papers

Wu H, (ed.), 2014, 'Lifetime holes aware register allocation for clustered VLIW processors.', in Proceedings -Design, Automation and Test in Europe, DATE, IEEE, presented at Design, Automation & Test in Europe Conference & Exhibition, DATE 2014,, Dresden, Germany, 24 - 28 March 2014, http://dx.doi.org/10.7873/DATE2014.103

Wu H, 2014, 'Randomised Multipath Routing for Secure Data Collection', in The IEEE Ninth International Conference on Intelligent Sensors, Sensor Networks and Information Processing, presented at The IEEE Ninth International Conference on Intelligent Sensors, Sensor Networks and Information Processing, Singapore, 21 - 24 April 2014, http://dx.doi.org/10.1109/ISSNIP.2014.6827598

Zhang X; Wu H; Sun H, 2013, 'Register allocation by incremental graph colouring for clustered VLIW processors', in Proceedings - 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications, TrustCom 2013, pp. 927 - 934, http://dx.doi.org/10.1109/TrustCom.2013.113

Wan Q; Wu H; Xue J, 2012, 'WCET-aware data selection and allocation for scratchpad memory', in ACM SIGPLAN Notices, pp. 41 - 50

Wu H; Mahmud S, 2012, 'A 2-approximation algorithm for optimal deployment of k base stations in WSNs', in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), pp. 378 - 391, http://dx.doi.org/10.1007/978-3-642-30054-7_30

Mahmud S; Wu H; Xue J, 2011, 'Efficient energy balancing aware multiple base station deployment for WSNs', in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), pp. 179 - 194, http://dx.doi.org/10.1007/978-3-642-19186-2_12

Li A; Wu H; Feng H; Xue J, 2007, 'Towards data tiling for whole programs in scratchpad memory allocation', in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), pp. 63 - 74

Wu H; Parameswaran S, 2006, 'Minimising the energy consumption of real-time tasks with precedence constraints on a single processor', in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), pp. 45 - 56

Wu H; Jaffar J; Xue J, 2006, 'Instruction scheduling with release times and deadlines on ILP processors', in Proceedings - 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2006, pp. 51 - 60, http://dx.doi.org/10.1109/RTCSA.2006.39|

Wu H; Jaffar J, 2002, 'Two Processor Scheduling with Real Release Times and Deadlines', in 14th International ACM Symposium on Parallel Algorithms and Architectures, presented at 14th International ACM Symposium on Parallel Algorithms and Architectures, Winnipeg, Canada, 11 - 13 August 2002

Wu H; Jaffar J, 2001, 'An Efficient Algorithm for Scheduling Instructions with Deadline Constraints on ILP Processors', in 22nd IEEE Real-TIme Symposium, presented at 22nd IEEE Real-TIme Symposium, London, England, 2 - 5 December 2001

Wu H; Jaffar J; Yap R, 2001, 'Instruction Scheduling with Timing Constraints on a Single RISC processor with 0/1 Latencies', in 6th International Conference on Principles and Practice of Constraints Programming, presented at 6th International Conference on Principles and Practice of Constraints Programming, Singapore, 18 - 21 September 2000

Wu H; Jaffar J; Yap R, 2000, 'A Fast Algorithm for Scheduling Instructions with Deadline Constraints on RISC Machines', in 2000 International Conference on Parallel Architectures and Compilation Techniques, presented at International Conference on Parallel Architectures and Compilation Techniques 2000, Philadelphia, Pennsylvania, 15 - 19 October 2000


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