Select Publications

by Professor Jingling Xue

Books

Xue J, 2000, Loop Tiling for Parallelism, Kluwer Academic Publishers, Boston

Book Chapters

Xue J; Huang Q, 2006, 'Code Tiling: One Size Fits All', in High-Performance Computing: Paradigm and Infrastructure, pp. 219 - 240, http://dx.doi.org/10.1002/0471732710.ch11

Xue J; Huang Q, 2005, 'Code tiling: One size fits all', in High-Performance Computing: Paradigm and Infrastructure, pp. 219 - 240, http://dx.doi.org/10.1002/0471732710.ch11

Journal articles

Su Y; Ye D; Xue J; Liao XK, 2016, 'An Efficient GPU Implementation of Inclusion-Based Pointer Analysis', IEEE Transactions on Parallel and Distributed Systems, vol. 27, no. 2, pp. 353 - 366, http://dx.doi.org/10.1109/TPDS.2015.2397933

Chen J; Yang X; Dong Y; Tang Y; Xue J; Wang Z; Zhou W, 2016, 'Reducing Static Energy in Supercomputer Interconnection Networks Using Topology-Aware Partitioning', IEEE Transactions on Computers, pp. 1 - 1, http://dx.doi.org/10.1109/TC.2015.2493523

Zhao J; Cui H; Xue J; Feng X, 2016, 'Predicting Cross-Core Performance Interference on Multicore Processors with Regression Analysis', IEEE Transactions on Parallel and Distributed Systems, vol. 27, no. 5, pp. 1443 - 1456, http://dx.doi.org/10.1109/TPDS.2015.2442983

Wang L; Liao XK; Xue JL; Weil S; Wen YC; Yang XJ, 2015, 'Enhancement of cooperation between file systems and applications — on VFS extensions for optimized performance', Science China Information Sciences, vol. 58, no. 9, http://dx.doi.org/10.1007/s11432-014-5181-x

Wang L; Xue J; Yang X, 2014, 'Acyclic orientation graph coloring for software-managed memory allocation', Science China Information Sciences, http://dx.doi.org/10.1007/s11432-014-5131-7

Liao XK; Yung CQ; Tang T; Yi HZ; Wang F; Wu Q; Xue J, 2014, 'OpenMC: Towards simplifying programming for tianhe supercomputers', Journal of Computer Science and Technology, vol. 29, no. 3, pp. 532 - 546, http://dx.doi.org/10.1007/s11390-014-1447-4

Sui Y; Ye D; Xue J, 2014, 'Detecting memory leaks statically with full-sparse value-flow analysis', IEEE Transactions on Software Engineering, vol. 40, no. 2, pp. 107 - 122, http://dx.doi.org/10.1109/TSE.2014.2302311

Sui Y; Ye S; Xue J; Zhang J, 2014, 'Making context-sensitive inclusion-based pointer analysis practical for compilers using parameterised summarisation', Software: Practice and Experience, vol. 44, no. 12, pp. 1485 - 1510, http://dx.doi.org/10.1002/spe.2214

Franke B; Xue J, 2013, 'Foreword', Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), pp. iii

Yang C-Q; Wu Q; Tang T; Wang F; Xue J-L, 2013, 'Programming for scientific computing on peta-scale heterogeneous parallel systems', Journal of Central South University, vol. 20, no. 5, pp. 1189 - 1203, http://dx.doi.org/10.1007/s11771-013-1602-z

Franke B; Xue J, 2013, 'Foreword', ACM SIGPLAN Notices, vol. 48, no. 5, pp. iii

Li J; Xue J; Xie X; Wan Q; Tan Q; Tan L, 2013, 'Epipe: A low-cost fault-tolerance technique considering WCET constraints', Journal of Systems Architecture, vol. 59, no. 10, pp. 1383 - 1393, http://dx.doi.org/10.1016/j.sysarc.2013.06.003

Zhang X; Wu H; Xue J, 2013, 'Instruction scheduling with k-successor tree for clustered VLIW processors', Design Automation for Embedded Systems, vol. 17, no. 2, pp. 439 - 458, http://dx.doi.org/10.1007/s10617-012-9103-0

Liu D; Wang Y; Shao Z; Guo M; Xue J, 2012, 'Optimally Maximizing Iteration-Level Loop Parallelism', IEEE Transactions on Parallel and Distributed Systems, vol. 23, no. 3, pp. 564 - 572, http://dx.doi.org/10.1109/TPDS.2011.171

Wang L; Xue J; Yang X, 2012, 'Optimizing modulo scheduling to achieve reuse and concurrency for stream processors', Journal of Supercomputing, vol. 59, no. 3, pp. 1229 - 1251, http://dx.doi.org/10.1007/s11227-010-0522-z

Di P; Wu H; Xue J; Wang F; Yang C, 2012, 'Parallelizing SOR for GPGPUs using alternate loop tiling', Parallel Computing, vol. 38, no. 6-7, pp. 310 - 328, http://dx.doi.org/10.1016/j.parco.2012.03.004

Guan Y; Xue J, 2011, 'Leakage-aware modulo scheduling for embedded VLIW processors', Journal of Computer Science and Technology, vol. 26, no. 3, pp. 405 - 417, http://dx.doi.org/10.1007/s11390-011-1143-6

Gao L; Ngai T; Xue J, 2010, 'Loop Recreation for Thread-Level Speculation on Multicore Processors', Software: Practice and Experience, vol. 40, no. 1, pp. 45 - 72, http://dx.doi.org/10.1002/spe.v40:1

Gao L; Xue J; Ngai T-F, 2009, 'Loop recreation for thread-level speculation on multicore processors', Software: Practice and Experience, pp. n/a - n/a, http://dx.doi.org/10.1002/spe.947

Mi W; Feng X-B; Jia Y-C; Chen L; Xue J-L, 2009, 'PARBLO: Page-Allocation-Based DRAM Row Buffer Locality Optimization', Journal of Computer Science and Technology, vol. 24, no. 6, pp. 1086 - 1097, http://dx.doi.org/10.1007/s11390-009-9297-1

Li L; Feng H; Xue J, 2009, 'Compiler-directed scratchpad memory management via graph coloring', ACM Transactions on Architecture and Code Optimization, vol. 6, no. 3, pp. 1 - 17, http://dx.doi.org/10.1145/1582710.1582711

Lenders P; Xue J, 2008, 'Factorization of singular integer matrices', Linear Algebra and Its Applications, vol. 428, no. 4, pp. 1046 - 1055, http://dx.doi.org/10.1016/j.laa.2007.09.012

Xue J; Guo M; Wei D, 2008, 'Improving the parallelism of iterative methods by aggressive loop fusion', Journal of Supercomputing, vol. 43, no. 2, pp. 147 - 164, http://dx.doi.org/10.1007/s11227-007-0124-6

Scholz B; Burgstaller B; Xue J, 2008, 'Minimal placement of bank selection instructions for partitioned memory architectures', ACM Transactions on Embedded Computing Systems, vol. 7, no. 2, pp. 1 - 32, http://dx.doi.org/10.1145/1331331.1331336

Vera X; Lisper B; Xue J, 2007, 'Data cache locking for tight timing calculations', ACM Transactions on Embedded Computing Systems, vol. 7, no. 1, pp. 1 - 38, http://dx.doi.org/10.1145/1324969.1324973

Xue J; Nguyen PH; Potter J, 2007, 'Interprocedural side-effect analysis for incomplete object-oriented software modules', Journal of Systems and Software, vol. 80, no. 1, pp. 92 - 105, http://dx.doi.org/10.1016/j.jss.2006.06.015

Li L; Xue J, 2007, 'Trace-based leakage energy optimisations at link time', Journal of Systems Architecture, vol. 53, no. 1, pp. 1 - 20, http://dx.doi.org/10.1016/j.sysarc.2006.05.002

Xue J; Cai Q, 2006, 'A lifetime optimal algorithm for speculative PRE', ACM Transactions on Architecture and Code Optimization, vol. 3, no. 2, pp. 115 - 155, http://dx.doi.org/10.1145/1138035.1138036

Xue J; Cai Q; Gao L, 2006, 'Partial dead code elimination on predicated code regions', Software: Practice and Experience, vol. 36, no. 15, pp. 1655 - 1685, http://dx.doi.org/10.1002/spe.739

Gentile A; Verdoscia L; Vitabile S; Abderazek BA; Yang LT; Audsley N; Cai X; Cao J; Chai SM; Chang N; Cheng A; Fanucci L; Givargis T; Gomes L; Gupta R; Hassan H; Hsiao MS; Hsiung PA; Joe K; John E; Kastner R; Kwok YK; Lee YH; Leporati F; Lopez-Lagunas A; Li T; Liao SW; Lin M; Macii A; Nakano K; Navet N; O'Donnell J; Robinson WH; Shao Z; Sorbello F; Taha T; Wang F; Scott Wills D; Wills LM; Xue J; Zhang F; Zhang Y; Zhou H; Zhu D; Zhu Y; Marinoni M; Foglia P, 2006, 'Message from IWEC workshop co-chairs', Proceedings of the International Conference on Parallel Processing Workshops, pp. xvii - xviii, http://dx.doi.org/10.1109/ICPPW.2006.47

Zhu M; Yang LT; Touriño J; Pan L; Brent RP; Dongarra J; Gustafson J; Joubert G; Pan Y; Zhang X; Abawajy JH; Aubanel E; Bahi J; Banicescu I; Bhalla S; Bic LF; Biswas R; Bourgeois A; Buecker M; Cabaleiro JC; Cai X; Carretero J; Chen J; Dai Y; De Mello R; Dillencourt MB; Di Martino B; Doallo R; Doncescu A; Gravvanis GA; Huang CH; Ierotheou C; Jie W; Karatza H; Koziris N; Lei Z; Leng T; Li Y; Martin MJ; Michielse PH; Narravula H; Ng MK; Ni J; O'Donnell J; Quintana-Orti E; Rauber T; Runger G; Salem FA; Sarker BK; Sedukhin SG; Shi H; Skjellum T; Strazdins P; Thulasiram RK; Tian X; Tomko K; Van Engelen R; Verdoscia L; Wu J; Xiao B; Xu C; Xue J; Yang X; Zheng Y; Zhou B; Zhou X; Zlatev Z; Cariño R; Couturier R; Guo Z; Wang Y; Ding M; Zekri A, 2006, 'Message from HPSEC workshop co-chairs', Proceedings of the International Conference on Parallel Processing Workshops, pp. xix - xxi, http://dx.doi.org/10.1109/ICPPW.2006.46

Jingling Xue; Vera X, 2004, 'Efficient and accurate analytical modeling of whole-program data cache behavior', IEEE Transactions on Computers, vol. 53, no. 5, pp. 547 - 566_3, http://dx.doi.org/10.1109/TC.2004.1275296

Xue J; Lenders P, 2002, 'Space-Time Equations for Non-Unimodular Mappings', International Journal of Computer Mathematics, vol. 79, no. 5, pp. 555 - 572, http://dx.doi.org/10.1080/00207160210953

Xue J; Cai W, 2002, 'Time-minimal tiling when rise is larger than zero', Parallel Computing, vol. 28, no. 6, pp. 915 - 939, http://dx.doi.org/10.1016/S0167-8191(02)00098-4

Xue J, 2002, 'Eigenvectors-Based Parallelisation of Nested Loops with Affine Dependences', International Journal of Parallel, Emergent and Distributed Systems, pp. 237 - 248

Xue J, 2002, 'Space-Time Equations for Non-Unimodular Mappings', International Journal of Computer Mathematics, pp. 552 - 572

Tang P; Xue J, 2000, 'Generating efficient tiled code for distributed memory machines', Parallel Computing, vol. 26, no. 11, pp. 1369 - 1410, http://dx.doi.org/10.1016/S0167-8191(00)00040-5

Chen S; Xue J, 1999, 'Partitioning and scheduling loops on NOWs', Computer Communications, vol. 22, no. 11, pp. 1017 - 1033, http://dx.doi.org/10.1016/S0140-3664(99)00073-0

Conference Papers

Xue J; Fan X; Sui Y, 2016, 'Contention-Aware Scheduling for Asymmetric Multicore Processors.', in 2015 IEEE 21st International Conference on Parallel and Distributed Systems (ICPADS), pp. 742 - 751, presented at 2015 IEEE 21st International Conference on Parallel and Distributed Systems (ICPADS), Melbourne, 14 - 17 December 2015, http://dx.doi.org/10.1109/ICPADS.2015.98

Zhou H; Xue JL, 2016, 'Exploiting Mixed SIMD Parallelism by Reducing Data Reorganization Overhead', presented at International symposium on code generation and optimization, Barcelona, Spain, 12 - 18 March 2016

Moore RW; Childers BR; Xue J, 2015, 'Performance modeling of multithreaded programs for mobile asymmetric chip multiprocessors', in Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th Inter, pp. 957 - 963, http://dx.doi.org/10.1109/HPCC-CSS-ICESS.2015.151

Xue J, 2015, 'Design and Implementation of a Highly Efficient DGEMM for 64-bit ARMv8 Multi-Core Processors', in 2015 International Conference on Parallel Processing, presented at 2015 International Conference on Parallel Processing, Beijing, 1 - 4 September 2015, http://dx.doi.org/10.1109/ICPP.2015.29

He W; Cui H; Lu B; Zhao J; Li S; Ruan G; Xue J; Feng X; Yang W; Yan Y, 2015, 'Hadoop+: Modeling and evaluating the heterogeneity for MapReduce applications in heterogeneous clusters', in Proceedings of the International Conference on Supercomputing, pp. 143 - 153, http://dx.doi.org/10.1145/2751205.2751236

Li Y; Tan T; Xue J, 2015, 'Effective soundness-guided reflection analysis', in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), pp. 162 - 180, http://dx.doi.org/10.1007/978-3-662-48288-9_10

Wang Y; Wang T; Shao Z; Liu D; Xue J, 2015, 'File system-independent block device support for storage class memory', in Proceedings - IEEE INFOCOM, pp. 468 - 473, http://dx.doi.org/10.1109/INFCOMW.2015.7179429

Di P; Sui Y; Ye D; Xue J, 2015, 'Region-Based May-Happen-in-Parallel Analysis for C Programs', pp. 889 - 898, presented at 2015 44th International Conference on on Parallel Processing (ICPP), Beijing China, 1 - 4 September 2015, http://dx.doi.org/10.1109/ICPP.2015.98

Su Y; Ye D; Xue J, 2014, 'Parallel pointer analysis with CFL-reachability', in Proceedings of the International Conference on Parallel Processing, pp. 451 - 460, http://dx.doi.org/10.1109/ICPP.2014.54


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