Select Publications by Professor Jingling Xue


Xue J, 2000, Loop Tiling for Parallelism, Original, Kluwer Academic Publishers, Boston

Book Chapters

Xue J; Huang Q, 2006, 'Code Tiling: One Size Fits All', in High-Performance Computing: Paradigm and Infrastructure, pp. 219 - 240, 10.1002/0471732710.ch11

Lengauer C; Xue J, 1994, 'Adapting a sequential algorithm for a systolic design', in Transformational Approaches to Systolic Design, Chapman & Hall, pp. 179 - 204,*Version*=1&*entries*=0

Xue J; Lengauer C, 1991, 'Specifying control signals for one-dimensional systolic arrays by uniform recurrence equations', in Algorithms and Parallel VLSI Architectures II, Elsevier, pp. 181 - 187,

Journal articles

Wang Y; Wang T; Liu D; Shao Z; Xue J, 2016, 'Fine grained, direct access file system support for storage class memory', Journal of Systems Architecture, 10.1016/j.sysarc.2016.07.003

Zhao J; Cui H; Xue J; Feng X, 2016, 'Predicting Cross-Core Performance Interference on Multicore Processors with Regression Analysis', IEEE Transactions on Parallel and Distributed Systems, vol. 27, pp. 1443 - 1456, 10.1109/TPDS.2015.2442983

Chen J; Tang Y; Dong Y; Xue J; Wang Z; Zhou W, 2016, 'Reducing Static Energy in Supercomputer Interconnection Networks Using Topology-Aware Partitioning', IEEE Transactions on Computers, vol. 65, pp. 2588 - 2602, 10.1109/TC.2015.2493523

Liu D; Zhong K; Wang T; Wang Y; Shao Z; Sha E; Xue J, 2016, 'Durable Address Translation in PCM-based Flash Storage Systems', IEEE Transactions on Parallel and Distributed Systems, pp. 1 - 1, 10.1109/TPDS.2016.2586059

Su Y; Ye D; Xue J; Liao XK, 2016, 'An Efficient GPU Implementation of Inclusion-Based Pointer Analysis', IEEE Transactions on Parallel and Distributed Systems, vol. 27, pp. 353 - 366, 10.1109/TPDS.2015.2397933

Zhou H; Xue J, 2016, 'A compiler approach for exploiting partial SIMD parallelism', ACM Transactions on Architecture and Code Optimization, vol. 13, pp. 11:1 - 11:26, 10.1145/2886101

Sui Y; Ye D; Su Y; Xue J, 2016, 'Eliminating Redundant Bounds Checks in Dynamic Buffer Overflow Detection Using Weakest Preconditions', IEEE Transactions on Reliability, vol. PP, pp. 1 - 18, 10.1109/TR.2016.2570538

Wang L; Liao XK; Xue JL; Weil S; Wen YC; Yang XJ, 2015, 'Enhancement of cooperation between file systems and applications — on VFS extensions for optimized performance', Science China Information Sciences, vol. 58, 10.1007/s11432-014-5181-x

Sui Y; Ye S; Xue J; Zhang J, 2014, 'Making context-sensitive inclusion-based pointer analysis practical for compilers using parameterised summarisation', Software: Practice and Experience, vol. 44, pp. 1485 - 1510, 10.1002/spe.2214

Sui Y; Ye D; Xue J, 2014, 'Detecting memory leaks statically with full-sparse value-flow analysis', IEEE Transactions on Software Engineering, vol. 40, pp. 107 - 122, 10.1109/TSE.2014.2302311

Liao XK; Yung CQ; Tang T; Yi HZ; Wang F; Wu Q; Xue J, 2014, 'OpenMC: Towards simplifying programming for tianhe supercomputers', Journal of Computer Science and Technology, vol. 29, pp. 532 - 546, 10.1007/s11390-014-1447-4

Wang L; Xue JL; Yang XJ, 2014, 'Acyclic orientation graph coloring for software-managed memory allocation', Science China Information Sciences, vol. 57, pp. 1 - 18, 10.1007/s11432-014-5131-7

Zhang X; Wu H; Xue J, 2013, 'Instruction scheduling with k-successor tree for clustered VLIW processors', Design Automation for Embedded Systems, vol. 17, pp. 439 - 458, 10.1007/s10617-012-9103-0

Yang C-Q; Wu Q; Tang T; Wang F; Xue J-L, 2013, 'Programming for scientific computing on peta-scale heterogeneous parallel systems', Journal of Central South University, vol. 20, pp. 1189 - 1203, 10.1007/s11771-013-1602-z

Li J; Xue J; Xie X; Wan Q; Tan Q; Tan L, 2013, 'Epipe: A low-cost fault-tolerance technique considering WCET constraints', Journal of Systems Architecture, vol. 59, pp. 1383 - 1393, 10.1016/j.sysarc.2013.06.003

Wang L; Xue J; Yang X, 2012, 'Optimizing modulo scheduling to achieve reuse and concurrency for stream processors', Journal of Supercomputing, vol. 59, pp. 1229 - 1251, 10.1007/s11227-010-0522-z

Liu D; Wang Y; Shao Z; Guo M; Xue J, 2012, 'Optimally Maximizing Iteration-Level Loop Parallelism', IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, vol. 23, pp. 564 - 572, 10.1109/TPDS.2011.171

Di P; Wu H; Xue J; Wang F; Yang C, 2012, 'Parallelizing SOR for GPGPUs using alternate loop tiling', Parallel Computing, vol. 38, pp. 310 - 328, 10.1016/j.parco.2012.03.004

Gao L; Xue J; Ngai T-F, 2009, 'Loop recreation for thread-level speculation on multicore processors', Software: Practice and Experience, pp. 45 - 72, 10.1002/spe.947

Mi W; Feng X-B; Jia Y-C; Chen L; Xue J-L, 2009, 'PARBLO: Page-Allocation-Based DRAM Row Buffer Locality Optimization', Journal of Computer Science and Technology, vol. 24, pp. 1086 - 1097, 10.1007/s11390-009-9297-1

Li L; Feng H; Xue J, 2009, 'Compiler-directed scratchpad memory management via graph coloring', ACM Transactions on Architecture and Code Optimization, vol. 6, pp. 1 - 17, 10.1145/1582710.1582711

Lenders P; Xue J, 2008, 'Factorization of singular integer matrices', Linear Algebra and its Applications, vol. 428, pp. 1046 - 1055, 10.1016/j.laa.2007.09.012

Xue J; Guo M; Wei D, 2008, 'Improving the parallelism of iterative methods by aggressive loop fusion', The Journal of Supercomputing, vol. 43, pp. 147 - 164, 10.1007/s11227-007-0124-6

Scholz B; Burgstaller B; Xue J, 2008, 'Minimal placement of bank selection instructions for partitioned memory architectures', ACM Transactions on Embedded Computing Systems, vol. 7, pp. 1 - 32, 10.1145/1331331.1331336

Vera X; Lisper B; Xue J, 2007, 'Data cache locking for tight timing calculations', ACM Transactions on Embedded Computing Systems, vol. 7, pp. 1 - 38, 10.1145/1324969.1324973

Xue J; Nguyen PH; Potter J, 2007, 'Interprocedural side-effect analysis for incomplete object-oriented software modules', Journal of Systems and Software, vol. 80, pp. 92 - 105, 10.1016/j.jss.2006.06.015

Li L; Xue J, 2007, 'Trace-based leakage energy optimisations at link time', Journal of Systems Architecture, vol. 53, pp. 1 - 20, 10.1016/j.sysarc.2006.05.002

Xue J; Cai Q, 2006, 'A lifetime optimal algorithm for speculative PRE', ACM Transactions on Architecture and Code Optimization, vol. 3, pp. 115 - 155, 10.1145/1138035.1138036

Xue J; Cai Q; Gao L, 2006, 'Partial dead code elimination on predicated code regions', Software: Practice and Experience, vol. 36, pp. 1655 - 1685, 10.1002/spe.739

Jingling Xue; Vera X, 2004, 'Efficient and accurate analytical modeling of whole-program data cache behavior', IEEE Transactions on Computers, vol. 53, pp. 547 - 566_3, 10.1109/TC.2004.1275296

Xue J; Lenders P, 2002, 'Space-Time Equations for Non-Unimodular Mappings', International Journal of Computer Mathematics, vol. 79, pp. 555 - 572, 10.1080/00207160210953

Xue J; Cai W, 2002, 'Time-minimal tiling when rise is larger than zero', Parallel Computing, vol. 28, pp. 915 - 939, 10.1016/S0167-8191(02)00098-4

Xue J, 2002, 'Eigenvectors-Based Parallelisation of Nested Loops with Affine Dependences', Parallel Algorithms and Applications, pp. 237 - 248

Tang P; Xue J, 2000, 'Generating efficient tiled code for distributed memory machines', Parallel Computing, vol. 26, pp. 1369 - 1410, 10.1016/S0167-8191(00)00040-5

Chen S; Xue J, 1999, 'Partitioning and scheduling loops on NOWs', Computer Communications, vol. 22, pp. 1017 - 1033, 10.1016/S0140-3664(99)00073-0

Xue J; Huang C-H, 1998, 'Reuse-Driven Tiling for Improving Data Locality', International Journal of Parallel Programming, vol. 26, 10.1023/A:1018734612524

Xue J, 1997, 'Unimodular transformations of non-perfectly nested loops', Parallel Computing, vol. 22, pp. 1621 - 1645, 10.1016/S0167-8191(96)00063-4

Xue J, 1997, 'On Tiling as a Loop Transformation', Parallel Processing Letters, vol. 07, pp. 409 - 424, 10.1142/S0129626497000401

Xue J, 1997, 'Communication-Minimal Tiling of Uniform Dependence Loops', Journal of Parallel and Distributed Computin, vol. 42, pp. 42 - 59, 10.1006/jpdc.1997.1310

Xue J, 1996, 'Transformations of nested loops with non-convex iteration spaces', Parallel Computing, vol. 22, pp. 339 - 368, 10.1016/0167-8191(95)00069-0

Xue J, 1996, 'GENERALISING THE UNIMODULAR APPROACH TO RESTRUCTURE IMPERFECTLY NESTED LOOPS', Parallel Processing Letters, vol. 06, pp. 401 - 414, 10.1142/S0129626496000388

Xue J, 1995, 'Closed-form mapping conditions for the synthesis of linear processor arrays', Journal of VLSI signal processing systems for signal, image and video technology, vol. 10, pp. 181 - 199, 10.1007/BF02407035

Xue J, 1994, 'Automating non-unimodular loop transformations for massive parallelism', Parallel Computing, vol. 20, pp. 711 - 728, 10.1016/0167-8191(94)90002-7

Xue J; Lengauer C, 1992, 'The synthesis of control signals for one-dimensional systolic arrays', Integration, the VLSI Journal, vol. 14, pp. 1 - 32, 10.1016/0167-9260(92)90008-M

Lengauer C; Xue J, 1991, 'A systolic array for pyramidal algorithms', Journal of VLSI signal processing systems for signal, image and video technology, vol. 3, pp. 237 - 257, 10.1007/BF00925834

XUE JINGLING, 1991, 'SPECIFYING CONTROL SIGNALS FOR SYSTOLIC ARRAYS BY UNIFORM RECURRENCE EQUATIONS', Parallel Processing Letters, vol. 01, pp. 83 - 93, 10.1142/S0129626491000033


Back to profile page