Select Publications by Professor Jingling Xue


Srikanthan T; Xue J; Chang CH, 2005, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics: Preface

Yew PC; Xue J, 2004, Preface

Xue J, 2000, Loop Tiling for Parallelism, Original, Kluwer Academic Publishers, Boston

Book Chapters

Xue J; Huang Q, 2006, 'Code Tiling: One Size Fits All', in High-Performance Computing: Paradigm and Infrastructure, pp. 219 - 240,

Lengauer C; Xue J, 1994, 'Adapting a sequential algorithm for a systolic design', in Transformational Approaches to Systolic Design, Chapman & Hall, pp. 179 - 204,*Version*=1&*entries*=0

Xue J; Lengauer C, 1991, 'Specifying control signals for one-dimensional systolic arrays by uniform recurrence equations', in Algorithms and Parallel VLSI Architectures II, Elsevier, pp. 181 - 187,

Journal articles

Sui Y; Ye D; Su Y; Xue J, 2016, 'Eliminating Redundant Bounds Checks in Dynamic Buffer Overflow Detection Using Weakest Preconditions', IEEE Transactions on Reliability,

Wang Y; Wang T; Liu D; Shao Z; Xue J, 2016, 'Fine grained, direct access file system support for storage class memory', Journal of Systems Architecture,

Zhao J; Cui H; Xue J; Feng X, 2016, 'Predicting Cross-Core Performance Interference on Multicore Processors with Regression Analysis', IEEE Transactions on Parallel and Distributed Systems, vol. 27, pp. 1443 - 1456,

Chen J; Tang Y; Dong Y; Xue J; Wang Z; Zhou W, 2016, 'Reducing Static Energy in Supercomputer Interconnection Networks Using Topology-Aware Partitioning', IEEE Transactions on Computers, vol. 65, pp. 2588 - 2602,

Liu D; Zhong K; Wang T; Wang Y; Shao Z; Sha E; Xue J, 2016, 'Durable Address Translation in PCM-based Flash Storage Systems', IEEE Transactions on Parallel and Distributed Systems, pp. 1 - 1,

Su Y; Ye D; Xue J; Liao XK, 2016, 'An Efficient GPU Implementation of Inclusion-Based Pointer Analysis', IEEE Transactions on Parallel and Distributed Systems, vol. 27, pp. 353 - 366,

Zhou H; Xue J, 2016, 'A compiler approach for exploiting partial SIMD parallelism', ACM Transactions on Architecture and Code Optimization, vol. 13, pp. 11:1 - 11:26,

Wang L; Liao XK; Xue JL; Weil S; Wen YC; Yang XJ, 2015, 'Enhancement of cooperation between file systems and applications — on VFS extensions for optimized performance', Science China Information Sciences, vol. 58,

Sui Y; Ye S; Xue J; Zhang J, 2014, 'Making context-sensitive inclusion-based pointer analysis practical for compilers using parameterised summarisation', Software: Practice and Experience, vol. 44, pp. 1485 - 1510,

Sui Y; Ye D; Xue J, 2014, 'Detecting memory leaks statically with full-sparse value-flow analysis', IEEE Transactions on Software Engineering, vol. 40, pp. 107 - 122,

Liao XK; Yung CQ; Tang T; Yi HZ; Wang F; Wu Q; Xue J, 2014, 'OpenMC: Towards simplifying programming for tianhe supercomputers', Journal of Computer Science and Technology, vol. 29, pp. 532 - 546,

Wang L; Xue JL; Yang XJ, 2014, 'Acyclic orientation graph coloring for software-managed memory allocation', Science China Information Sciences, vol. 57, pp. 1 - 18,

Zhang X; Wu H; Xue J, 2013, 'Instruction scheduling with k-successor tree for clustered VLIW processors', Design Automation for Embedded Systems, vol. 17, pp. 439 - 458,

Yang C-Q; Wu Q; Tang T; Wang F; Xue J-L, 2013, 'Programming for scientific computing on peta-scale heterogeneous parallel systems', Journal of Central South University, vol. 20, pp. 1189 - 1203,

Li J; Xue J; Xie X; Wan Q; Tan Q; Tan L, 2013, 'Epipe: A low-cost fault-tolerance technique considering WCET constraints', Journal of Systems Architecture, vol. 59, pp. 1383 - 1393,

Wang L; Xue J; Yang X, 2012, 'Optimizing modulo scheduling to achieve reuse and concurrency for stream processors', Journal of Supercomputing, vol. 59, pp. 1229 - 1251,

Liu D; Wang Y; Shao Z; Guo M; Xue J, 2012, 'Optimally Maximizing Iteration-Level Loop Parallelism', IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, vol. 23, pp. 564 - 572,

Di P; Wu H; Xue J; Wang F; Yang C, 2012, 'Parallelizing SOR for GPGPUs using alternate loop tiling', Parallel Computing, vol. 38, pp. 310 - 328,

Gao L; Xue J; Ngai T-F, 2009, 'Loop recreation for thread-level speculation on multicore processors', Software: Practice and Experience, pp. 45 - 72,

Mi W; Feng X-B; Jia Y-C; Chen L; Xue J-L, 2009, 'PARBLO: Page-Allocation-Based DRAM Row Buffer Locality Optimization', Journal of Computer Science and Technology, vol. 24, pp. 1086 - 1097,

Li L; Feng H; Xue J, 2009, 'Compiler-directed scratchpad memory management via graph coloring', ACM Transactions on Architecture and Code Optimization, vol. 6, pp. 1 - 17,

Lenders P; Xue J, 2008, 'Factorization of singular integer matrices', Linear Algebra and its Applications, vol. 428, pp. 1046 - 1055,

Xue J; Guo M; Wei D, 2008, 'Improving the parallelism of iterative methods by aggressive loop fusion', The Journal of Supercomputing, vol. 43, pp. 147 - 164,

Scholz B; Burgstaller B; Xue J, 2008, 'Minimal placement of bank selection instructions for partitioned memory architectures', ACM Transactions on Embedded Computing Systems, vol. 7, pp. 1 - 32,

Vera X; Lisper B; Xue J, 2007, 'Data cache locking for tight timing calculations', ACM Transactions on Embedded Computing Systems, vol. 7, pp. 1 - 38,

Xue J; Nguyen PH; Potter J, 2007, 'Interprocedural side-effect analysis for incomplete object-oriented software modules', Journal of Systems and Software, vol. 80, pp. 92 - 105,

Li L; Xue J, 2007, 'Trace-based leakage energy optimisations at link time', Journal of Systems Architecture, vol. 53, pp. 1 - 20,

Xue J; Cai Q, 2006, 'A lifetime optimal algorithm for speculative PRE', ACM Transactions on Architecture and Code Optimization, vol. 3, pp. 115 - 155,

Xue J; Cai Q; Gao L, 2006, 'Partial dead code elimination on predicated code regions', Software: Practice and Experience, vol. 36, pp. 1655 - 1685,

Jingling Xue; Vera X, 2004, 'Efficient and accurate analytical modeling of whole-program data cache behavior', IEEE Transactions on Computers, vol. 53, pp. 547 - 566_3,

Xue J; Lenders P, 2002, 'Space-Time Equations for Non-Unimodular Mappings', International Journal of Computer Mathematics, vol. 79, pp. 555 - 572,

Xue J; Cai W, 2002, 'Time-minimal tiling when rise is larger than zero', Parallel Computing, vol. 28, pp. 915 - 939,

Xue J, 2002, 'Eigenvectors-Based Parallelisation of Nested Loops with Affine Dependences', Parallel Algorithms and Applications, pp. 237 - 248

Tang P; Xue J, 2000, 'Generating efficient tiled code for distributed memory machines', Parallel Computing, vol. 26, pp. 1369 - 1410,

Chen S; Xue J, 1999, 'Partitioning and scheduling loops on NOWs', Computer Communications, vol. 22, pp. 1017 - 1033,

Xue J; Huang CH, 1998, 'Reuse-Driven Tiling for Improving Data Locality', International Journal of Parallel Programming, vol. 26, pp. 671 - 696

Xue J, 1997, 'Communication-Minimal Tiling of Uniform Dependence Loops', Journal of Parallel and Distributed Computing, vol. 42, pp. 42 - 59,

Xue J, 1997, 'On tiling as a loop transformation', Parallel Processing Letters, vol. 7, pp. 409 - 424

Xue J, 1997, 'Unimodular transformations of non-perfectly nested loops', Parallel Computing, vol. 22, pp. 1621 - 1645,

Xue J, 1997, 'On Tiling as a Loop Transformation', Parallel Processing Letters, vol. 07, pp. 409 - 424,

Xue J, 1996, 'Generalising the unimodular approach to restructure imperfectly nested loops', Parallel Processing Letters, vol. 6, pp. 401 - 414

Xue J, 1996, 'Transformations of nested loops with non-convex iteration spaces', Parallel Computing, vol. 22, pp. 339 - 368,


Xue J, 1995, 'Closed-form mapping conditions for the synthesis of linear processor arrays', Journal of VLSI signal processing systems for signal, image and video technology, vol. 10, pp. 181 - 199,


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