Select Publications
Journal articles
2023, '1LUTSensor: Detecting FPGA Voltage Fluctuations using LookUp Tables', IACR Transactions on Cryptographic Hardware and Embedded Systems, 2024, pp. 51 - 86, http://dx.doi.org/10.46586/tches.v2024.i1.51-86
,2023, 'Efficient end-to-end long-read sequence mapping using minimap2-fpga integrated with hardware accelerated chaining', Scientific Reports, 13, http://dx.doi.org/10.1038/s41598-023-47354-8
,2023, 'Flexible and efficient handling of nanopore sequencing signal data with slow5tools', Genome Biology, 24, http://dx.doi.org/10.1186/s13059-023-02910-3
,2023, 'ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 42, pp. 3505 - 3518, http://dx.doi.org/10.1109/TCAD.2023.3253045
,2023, 'Cross Layer Design Using HW/SW Co-Design and HLS to Accelerate Chaining in Genomic Analysis', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 42, pp. 2924 - 2937, http://dx.doi.org/10.1109/TCAD.2023.3236559
,2023, 'Special Issue: "Approximation at the Edge"', ACM Transactions on Embedded Computing Systems, 22, pp. 1 - 4, http://dx.doi.org/10.1145/3605757
,2023, 'Efficient real-time selective genome sequencing on resource-constrained devices', GigaScience, 12, http://dx.doi.org/10.1093/gigascience/giad046
,2022, 'A Power to Pulse Width Modulation Sensor for Remote Power Analysis Attacks', IACR Transactions on Cryptographic Hardware and Embedded Systems, 2022, pp. 589 - 613, http://dx.doi.org/10.46586/tches.v2022.i4.589-613
,2022, 'Fast nanopore sequencing data analysis with SLOW5', Nature Biotechnology, 40, pp. 1026 - 1029, http://dx.doi.org/10.1038/s41587-021-01147-4
,2021, 'COPS: A complete oblivious processing system', Microprocessors and Microsystems, 85, http://dx.doi.org/10.1016/j.micpro.2021.104295
,2021, 'QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks', ACM Transactions on Design Automation of Electronic Systems, 26, http://dx.doi.org/10.1145/3443706
,2021, 'UCloD: Small Clock Delays to Mitigate Remote Power Analysis Attacks', IEEE Access, 9, pp. 108411 - 108425, http://dx.doi.org/10.1109/ACCESS.2021.3100618
,2021, 'VITI: A Tiny Self-Calibrating Sensor for Power-Variation Measurement in FPGAs', IACR Transactions on Cryptographic Hardware and Embedded Systems, 2022, pp. 657 - 678, http://dx.doi.org/10.46586/tches.v2022.i1.657-678
,2021, 'SLOW5: a new file format enables massive acceleration of nanopore sequencing data analysis', , http://dx.doi.org/10.1101/2021.06.29.450255
,2021, 'SLOW5: a new file format enables massive acceleration of nanopore sequencing data analysis', , http://dx.doi.org/10.21203/rs.3.rs-668517/v1
,2020, 'GPU accelerated adaptive banded event alignment for rapid comparative nanopore signal analysis', BMC Bioinformatics, 21, http://dx.doi.org/10.1186/s12859-020-03697-x
,2020, 'Cache Friendly Optimisation of de Bruijn Graph Based Local Re-Assembly in Variant Calling', IEEE/ACM Transactions on Computational Biology and Bioinformatics, 17, pp. 1125 - 1133, http://dx.doi.org/10.1109/TCBB.2018.2881975
,2020, 'Fast Short Read De-Novo Assembly Using Overlap-Layout-Consensus Approach', IEEE/ACM Transactions on Computational Biology and Bioinformatics, 17, pp. 334 - 338, http://dx.doi.org/10.1109/TCBB.2018.2875479
,2020, 'Hardware Trojan mitigation in pipelined MPSoCs', ACM Transactions on Design Automation of Electronic Systems, 25, http://dx.doi.org/10.1145/3365578
,2019, 'Featherweight long read alignment using partitioned reference indexes', Scientific Reports, 9, pp. 4318, http://dx.doi.org/10.1038/s41598-019-40739-8
,2019, 'GPU Accelerated Adaptive Banded Event Alignment for Rapid Comparative Nanopore Signal Analysis', bioRxiv, http://dx.doi.org/10.1101/756122
,2019, 'Pairwise alignment of nucleotide sequences using maximal exact matches', BMC Bioinformatics, 20, pp. 261, http://dx.doi.org/10.1186/s12859-019-2827-0
,2018, 'Minimally biased multipliers for approximate integer and floating-point multiplication', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37, pp. 2623 - 2635, http://dx.doi.org/10.1109/TCAD.2018.2857262
,2018, 'Featherweight long read alignment using partitioned reference indexes', BIORXIV, http://dx.doi.org/10.1101/386847
,2018, 'Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD)', IEEE Design and Test, 35, pp. 101 - 102, http://dx.doi.org/10.1109/MDAT.2018.2799991
,2017, 'Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors', IEEE Transactions on Computers, 66, pp. 647 - 660, http://dx.doi.org/10.1109/TC.2016.2606378
,2017, 'Partial dynamic element matching technique for digital-to-analog converters used for digital harmonic-cancelling sine-wave synthesis', IEEE Transactions on Circuits and Systems I: Regular Papers, 64, pp. 296 - 309, http://dx.doi.org/10.1109/TCSI.2016.2613938
,2017, 'iCETD: An improved tag generation design for memory data authentication in embedded processor systems', Integration, the VLSI Journal, 56, pp. 96 - 104, http://dx.doi.org/10.1016/j.vlsi.2016.10.006
,2017, 'Improved VCF normalization for accurate VCF comparison.', Bioinformatics, 33, pp. 964 - 970, http://dx.doi.org/10.1093/bioinformatics/btw748
,2016, 'Processor design for soft errors: Challenges and state of the art', ACM Computing Surveys, 49, http://dx.doi.org/10.1145/2996357
,2016, 'Switchable cache: Utilising dark silicon for application specific cache optimisations', IET Computers and Digital Techniques, 10, pp. 157 - 164, http://dx.doi.org/10.1049/iet-cdt.2015.0114
,2016, 'Editorial Introduction of New Editor-in-Chief and Associate Editors', IEEE Embedded Systems Letters, 8, pp. 1, http://dx.doi.org/10.1109/LES.2016.2532418
,2015, 'Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34, pp. 1991 - 2003, http://dx.doi.org/10.1109/TCAD.2015.2445736
,2015, 'SecureD: A Secure Dual Core Embedded Processor', SecureD: A Secure Dual Core Embedded Processor, http://arxiv.org/abs/1511.01946v1
,2014, 'Energy-efficient adaptive pipelined MPSoCs for multimedia applications', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33, pp. 663 - 676, http://dx.doi.org/10.1109/TCAD.2014.2298196
,2014, 'Performance estimation of pipelined multiprocessor system-on-chips (MPSoCs)', IEEE Transactions on Parallel and Distributed Systems, 25, pp. 2159 - 2168, http://dx.doi.org/10.1109/TPDS.2013.268
,2012, 'Differential Power Analysis in AES: A Crypto Anatomy', IJEI: International Journal of Engineering and Industries, 2, pp. 118 - 130, http://www.aicit.org/ijei/global/paper_detail.html?jname=IJEI&q=46
,2012, 'Randomized Instruction Injection to Counter Power Analysis Attacks', ACM Transactions on Embedded Computing Systems (TECS), 11, pp. 28, http://dl.acm.org/citation.cfm?id=2345782
,2011, 'A hybrid hardware-software technique to improve reliability in embedded processors', ACM Transactions on Embedded Computing Systems (TECS), 10, pp. Article number: 36, http://dx.doi.org/10.1145/1952522.1952529
,2011, 'Architectural frameworks for security and reliability of MPSoCs', IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 19, pp. 1641 - 1654, http://dx.doi.org/10.1109/TVLSI.2010.2053856
,2011, 'Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks', IET Computers and Digital Techniques, 5, pp. 1 - 15, http://dx.doi.org/10.1049/iet-cdt.2009.0097
,2010, 'Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications', 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010, pp. 75 - 84
,2010, 'CASES 2009 guest editor's introduction', Design Automation for Embedded Systems, 14, pp. 285 - 286, http://dx.doi.org/10.1007/s10617-010-9060-4
,2010, 'Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29, pp. 1777 - 1789, http://dx.doi.org/10.1109/TCAD.2010.2061353
,2009, 'Custom floating-point unit generation for embedded systems', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28, pp. 638 - 650
,2009, 'Custom Floating-Point Unit Generation for Embedded Systems', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28, pp. 638 - 650
,2009, 'HMP-ASIP`s: heterogeneous multi-pipeline application-specific instruction-set processors', IET Computers and Digital Techniques, 3, pp. 94 - 108
,2009, 'Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis', ACM Transactions on Design Automation of Electronic Systems, 14
,2008, 'Architectural exploration of heterogeneous multiprocessor systems for JPEG', International Journal of Parallel Programming, 36, pp. 140 - 162, http://dx.doi.org/10.1007/s10766-007-0040-7
,2008, 'Embedded systems security - an overview', Design Automation for Embedded Systems, 12, pp. 173 - 183
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