Select Publications
By Dr Hui Guo
Conference Papers
, 2022, 'Holmes: An Efficient and Lightweight Semantic Based Anomalous Email Detector', in Proceedings - 2022 IEEE 21st International Conference on Trust, Security and Privacy in Computing and Communications, TrustCom 2022, pp. 1360 - 1367, http://dx.doi.org/10.1109/TrustCom56396.2022.00192
, 2022, 'HOLMES: An Efficient and Lightweight Semantic Based Anomalous Email Detector', in Proceedings - 2022 IEEE SmartWorld, Ubiquitous Intelligence and Computing, Autonomous and Trusted Vehicles, Scalable Computing and Communications, Digital Twin, Privacy Computing, Metaverse, SmartWorld/UIC/ATC/ScalCom/DigitalTwin/PriComp/Metaverse 2022, pp. 2293 - 2300, http://dx.doi.org/10.1109/SmartWorld-UIC-ATC-ScalCom-DigitalTwin-PriComp-Metaverse56740.2022.00326
, 2021, 'DualNet: Locate Then Detect Effective Payload with Deep Attention Network', in 2021 IEEE Conference on Dependable and Secure Computing, DSC 2021, http://dx.doi.org/10.1109/DSC49826.2021.9346261
, 2021, 'Hunter in the Dark: Discover Anomalous Network Activity Using Deep Ensemble Network', in IEEE International Conference on Software Quality, Reliability and Security, QRS, pp. 829 - 840, http://dx.doi.org/10.1109/QRS54544.2021.00092
, 2020, 'Densely Connected Residual Network for Attack Recognition', in Wang GJ; Ko R; Bhuiyan MZA; Pan Y (eds.), Proceedings - 2020 IEEE 19th International Conference on Trust, Security and Privacy in Computing and Communications, TrustCom 2020, Institute of Electrical and Electronics Engineers (IEEE), Guangzhou, China, pp. 233 - 242, presented at
, 2020, 'Pelican: A Deep Residual Network for Network Intrusion Detection', in Proceedings - 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN-W 2020, pp. 55 - 62, http://dx.doi.org/10.1109/DSN-W50199.2020.00018
, 2019, 'LuNet: A Deep Neural Network for Network Intrusion Detection', in 2019 IEEE Symposium Series on Computational Intelligence, SSCI 2019, pp. 617 - 624, http://dx.doi.org/10.1109/SSCI44817.2019.9003126
, 2019, 'A low performance-overhead ORAM design for processor system with un-trusted off-chip memory', in Proceedings of 2019 IEEE 2nd International Conference on Automation, Electronics and Electrical Engineering, AUTEEE 2019, pp. 315 - 321, http://dx.doi.org/10.1109/AUTEEE48671.2019.9033153
, 2019, 'A Transfer Learning Approach for Network Intrusion Detection', in 2019 4th IEEE International Conference on Big Data Analytics, ICBDA 2019, Institute of Electrical and Electronics Engineers (IEEE), pp. 281 - 285, presented at
, 2018, 'EETD: An energy efficient design for runtime hardware trojan detection in untrusted network-on-chip', in Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, pp. 345 - 350, http://dx.doi.org/10.1109/ISVLSI.2018.00070
, 2018, 'A Bandwidth-Aware Authentication Scheme for Packet-Integrity Attack Detection on Trojan Infected NoC', in IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, pp. 201 - 206, http://dx.doi.org/10.1109/VLSI-SoC.2018.8645051
, 2017, 'Packet leak detection on hardware-trojan infected NoCs for MPSoC systems', in ACM International Conference Proceeding Series, Wuhan, China, pp. 85 - 90, presented at
, 2016, 'Data-space relocation to improve data cache performance for embedded multi-threaded processor systems', in ACM International Conference Proceeding Series, pp. 193 - 197, http://dx.doi.org/10.1145/3033288.3033335
, 2016, 'EONS: Minimizing Energy Consumption for Executing Real-Time Workflows in Virtualized Cloud Data Centers', in Proceedings of the International Conference on Parallel Processing Workshops, pp. 385 - 392, http://dx.doi.org/10.1109/ICPPW.2016.60
, 2016, 'Improving tag generation for memory data authentication in embedded processor systems', in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 50 - 55, http://dx.doi.org/10.1109/ASPDAC.2016.7427988
, 2015, 'Effective Hardware-Level Thread Synchronization for High Performance and Power Efficiency in Application Specific Multithreaded Embedded Processors', New York City, USA, presented at
, 2014, 'Dynamic Encryption Key Design and Its Security Evaluation for Memory Data Protection in Embedded Systems', in Kim KJ (ed.), Beijing, presented at
, 2014, 'Energy-Aware Thread Scheduling for Embedded Multi-Threaded Processors: Architectural Level Design and Implementation', in Ghosal P (ed.), Proceedings IEEE Computer Society Annual Symposium on VLSI 2014, IEEE Computer Society Conference Publishing Services (CPS), Tampa, Florida, USA, pp. 178 - 183, presented at
, 2014, 'Dynamic encryption key design and its security evaluation for memory data protection in embedded systems', in 2014 International Conference on IT Convergence and Security, ICITCS 2014, http://dx.doi.org/10.1109/ICITCS.2014.7021759
, 2013, 'Evaluation of Multi-Threaded Processor Designs for Energy Efficient Embedded Systems', in 2013 IEEE 16th International Conference on Computational Science and Engineering (CSE 2013), IEEE Computer Society, Sydney, Australia, pp. 619 - 626, presented at
, 2012, 'A Cost-Effective Tag Design for Memory Data Authentication in Embedded Systems', in Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems, ACM, New York, NY, USA ©2012, pp. 17 - 26, presented at
, 2010, 'Enabling large decoded instruction loop caching for energy-aware embedded processors', in Proceedings of International Conference on Compilers Architectures and Synthesis for Embedded Systems (CASES), ACM, New York, USA, pp. 247 - 256, presented at
, 2010, 'An Energy Efficient Instruction Prefetching Scheme for Embedded Processors', in Proceedings of International Conference Ubiquitous Computing and Multimedia Applications, Springer, Germany, pp. 73 - 88, presented at
, 2009, 'ROBTIC: An On-Chip Instruction Cache Design for Low Power Embedded Systems', in Proceedings of the 15th IEEE International Conference on embedded and Real-time Computing Systems and Application, IEEE Computer Society, Beijing, China, presented at
, 2009, 'Computing marks for multiple assessors using adaptive averaging', in Proceedings of ICEE & ICEER 2009 Korea, Publishing Committee. ICEE & ICEER 2009, Korea, presented at
, 2009, 'Register File Customization for Low Power Embedded Processors', in Proceeding of the 2nd IEEE International Conference on Computer Science and Information Technology (IEEE ICCSIT 2009), IEEE Computer Society, Beijing , China, presented at
, 2009, 'A Segmental Bus-Invert Coding Method for Instruction Memory Data Bus Power Efficiency', in Proceeding of the 2009 IEEE International Symposium on Circuits and Systems (ISCAS 2009), IEEE CAS Society, Taipei, Taiwan, presented at
, 2008, 'Application Specific Low Power ALU Design', in 2008 IEEE/IFIP international conference on embedded and ubiquitous computing, Proceedings, Shanghai, China, presented at
, 2008, 'Security Design for Networked Multi-Service Smart Card Systems', in Proc. of the 2nd Intl. Conf. on Future Generation Communication and Networking (FGCN 2008), Sanya, China, presented at
, 2008, 'A VQ digital watermark algorithm based on T-mixture models segmentation', in 2008 IEEE International Conference Neural Networks and Signal Processing, ICNNSP, pp. 353 - 358, http://dx.doi.org/10.1109/ICNNSP.2008.4590371
, 2008, 'An algorithm for estimating number of components of Gaussian mixture model based on penalized distance', in 2008 International conference on neural networks and signal processing, Zhenjiang, China, presented at
, 2008, 'Security Design for Multi-Service Smart Card Systems', in FGCN: PROCEEDINGS OF THE 2008 SECOND INTERNATIONAL CONFERENCE ON FUTUREGENERATION COMMUNICATION AND NETWORKING, VOLS 1 AND 2, Ieee Computer Soc, Los Alamitos
, 2006, 'Application specific forwarding network and instruction encoding for multi-pipe ASIPs', in CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis, pp. 241 - 246, http://dx.doi.org/10.1145/1176254.1176313
, 2006, 'Customization of application specific heterogeneous multi-pipeline processors', in 43rd Design automation conference, Munich, Germany, presented at
, 2006, 'Customization of application specific heterogeneous multi-pipeline processors', in Proceedings of the Design Automation & Test in Europe Conference, IEEE, pp. 6 pp. - 6 pp., presented at
, 2005, 'Balancing system level pipelines with stage voltage scaling', in IEEE annual symposium on VLSI, Tampa, Florida, USA, presented at
, 2004, 'Dual-Pipeline Heterogeneous ASIP Design', in CODES + ISSS 2004, Stockholm, Sweden, presented at
, 1997, 'Partitioning of system level pipelines', in Proceedings of the Australian Microelectronics Conference, pp. 233 - 238
, 1997, 'Power reduction in pipelines', in Proceedings of the Australian Microelectronics Conference, pp. 239 - 244
, 1997, 'Unfolding loops with interdetermine count in system level pipelines', in Proceedings of the Australian Microelectronics Conference, pp. 82 - 87
, 1997, 'Power consumption in CMOS combinational logic blocks at high frequencies', in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 195 - 200