Select Publications
Preprints
2024, fence.t.s: Closing Timing Channels in High-Performance Out-of-Order Cores through ISA-Supported Temporal Partitioning
,2023, Proving the Absence of Microarchitectural Timing Channels, http://arxiv.org/abs/2310.17046v1
,2022, Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning, http://dx.doi.org/10.48550/arxiv.2202.12029
,2020, Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core, http://dx.doi.org/10.48550/arxiv.2005.02193
,2019, Can We Prove Time Protection?, http://dx.doi.org/10.48550/arxiv.1901.08338
,2018, Time Protection: the Missing OS Abstraction, http://dx.doi.org/10.48550/arxiv.1810.05345
,2018, Benchmarking Crimes: An Emerging Threat in Systems Security, http://dx.doi.org/10.48550/arxiv.1801.02381
,2016, Your Processor Leaks Information - and There's Nothing You Can Do About It, http://dx.doi.org/10.48550/arxiv.1612.04474
,2016, An Evaluation of Coarse-Grained Locking for Multicore Microkernels, http://dx.doi.org/10.48550/arxiv.1609.08372
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