By Scientia Professor Jingling Xue

Journal articles

Xue J, 2013, 'Session details: Programming language and implementation', ACM SIGPLAN Notices, 48, http://dx.doi.org/10.1145/3262901

Li J; Xue J; Xie X; Wan Q; Tan Q; Tan L, 2013, 'Epipe: A low-cost fault-tolerance technique considering WCET constraints', Journal of Systems Architecture, 59, pp. 1383 - 1393, http://dx.doi.org/10.1016/j.sysarc.2013.06.003

Zhang X; Wu H; Xue J, 2013, 'Instruction scheduling with k-successor tree for clustered VLIW processors', Design Automation for Embedded Systems, 17, pp. 439 - 458, http://dx.doi.org/10.1007/s10617-012-9103-0

Yang C-Q; Wu Q; Tang T; Wang F; Xue J-L, 2013, 'Programming for scientific computing on peta-scale heterogeneous parallel systems', Journal of Central South University, 20, pp. 1189 - 1203, http://dx.doi.org/10.1007/s11771-013-1602-z

Quan A; Xue J; Wielens J; Smillie KJ; Anggono V; Parker MW; Cousin MA; Graham ME; Robinson PJ, 2012, 'Phosphorylation of syndapin I F-BAR domain at two helix-capping motifs regulates membrane tubulation', Proceedings of the National Academy of Sciences of the United States of America, 109, pp. 3760 - 3765, http://dx.doi.org/10.1073/pnas.1108294109

Liu D; Wang Y; Shao Z; Guo M; Xue J, 2012, 'Optimally Maximizing Iteration-Level Loop Parallelism', IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 23, pp. 564 - 572, http://dx.doi.org/10.1109/TPDS.2011.171

Wang L; Xue J; Yang X, 2012, 'Optimizing modulo scheduling to achieve reuse and concurrency for stream processors', Journal of Supercomputing, 59, pp. 1229 - 1251, http://dx.doi.org/10.1007/s11227-010-0522-z

Wang L; Xue J; Yang X, 2012, 'Optimizing modulo scheduling to achieve reuse and concurrency for stream processors', Journal of Supercomputing, 59, pp. 1229 - 1251, http://dx.doi.org/10.1007/s11227-010-0522-z

Di P; Wu H; Xue J; Wang F; Yang C, 2012, 'Parallelizing SOR for GPGPUs Using Alternate Loop Tiling', Parallel Computing, 38, pp. 310 - 328, http://dx.doi.org/10.1016/j.parco.2012.03.004

Guan Y; Xue J, 2011, 'Leakage-aware modulo scheduling for embedded VLIW processors', Journal of Computer Science and Technology, 26, pp. 405 - 417, http://dx.doi.org/10.1007/s11390-011-1143-6

Chen H; Xue J; Zhang Y; Zhu X; Gao J; Yu B, 2009, 'Comparison of quantum dots immunofluorescence histochemistry and conventional immunohistochemistry for the detection of caveolin-1 and PCNA in the lung cancer tissue microarray', JOURNAL OF MOLECULAR HISTOLOGY, 40, pp. 261 - 268, http://dx.doi.org/10.1007/s10735-009-9237-y

Swain MV; Xue J, 2009, 'State of the art of Micro-CT applications in dental research.', International journal of oral science, 1, pp. 177 - 188, http://dx.doi.org/10.4248/IJOS09031

Li L; Feng H; Xue J, 2009, 'Compiler-directed scratchpad memory management via graph coloring', ACM Transactions on Architecture and Code Optimization, 6

Gao L; Xue J; Ngai T-F, 2009, 'Loop recreation for thread-level speculation on multicore processors', Software: Practice and Experience, pp. 45 - 72, http://dx.doi.org/10.1002/spe.947

Mi W; Feng X-B; Yao C; Chen L; Xue J, 2009, 'PARBLO: Page-Allocation-Based DRAM Row Buffer Locality Optimization', Journal of Computer Science and Technology, 24, pp. 1086 - 1097

Xue J; Lenders P, 2008, 'Factorization of singular integer matrices', Linear Algebra and its Applications, 428, pp. 1046 - 1055, http://dx.doi.org/10.1016/j.laa.2007.09.012

Xue J; Guo M; Wei D, 2008, 'Improving the parallelism of iterative methods by aggressive loop fusion', Journal of Supercomputing, 43, pp. 147 - 164, http://dx.doi.org/10.1007/s11227-007-0124-6

Scholz B; Burgstaller B; Xue J, 2008, 'Minimal placement of bank selection instructions for partitioned memory architectures', ACM Transactions on Embedded Computing Systems (TECS), 7, pp. 1 - 32, http://dx.doi.org/10.1145/1331331.1331336

Lian L; Quan HN; Jingling X, 2007, 'Scratchpad allocation for data aggregates in superperfect graphs', ACM SIGPLAN Notices, 42, pp. 207 - 216

Vera X; Lisper B; Xue J, 2007, 'Data cache locking for tight timing calculations', ACM Transactions on Embedded Computing Systems (TECS), 7, pp. 1 - 38

Xue J; Nguyen PH; Potter JM, 2007, 'Interprocedural side-effect analysis for incomplete object-oriented software modules', Journal of Systems and Software, 80, pp. 92 - 105, http://dx.doi.org/10.1016/j.jss.2006.06.015

Li L; Xue J, 2007, 'Trace-based leakage energy optimisations at link time', Journal of Systems Architecture, 53, pp. 1 - 20, http://dx.doi.org/10.1016/j.sysarc.2006.05.002

Zhu M; Yang LT; Touriño J; Pan L; Brent RP; Dongarra J; Gustafson J; Joubert G; Pan Y; Zhang X; Abawajy JH; Aubanel E; Bahi J; Banicescu I; Bhalla S; Bic LF; Biswas R; Bourgeois A; Buecker M; Cabaleiro JC; Cai X; Carretero J; Chen J; Dai Y; De Mello R; Dillencourt MB; Di Martino B; Doallo R; Doncescu A; Gravvanis GA; Huang CH; Ierotheou C; Jie W; Karatza H; Koziris N; Lei Z; Leng T; Li Y; Martin MJ; Michielse PH; Narravula H; Ng MK; Ni J; O'Donnell J; Quintana-Orti E; Rauber T; Runger G; Salem FA; Sarker BK; Sedukhin SG; Shi H; Skjellum T; Strazdins P; Thulasiram RK; Tian X; Tomko K; Van Engelen R; Verdoscia L; Wu J; Xiao B; Xu C; Xue J; Yang X; Zheng Y; Zhou B; Zhou X; Zlatev Z; Cariño R; Couturier R; Guo Z; Wang Y; Ding M; Zekri A, 2006, 'Message from HPSEC workshop co-chairs', Proceedings of the International Conference on Parallel Processing Workshops, http://dx.doi.org/10.1109/ICPPW.2006.46

Bordim J; Cai X; Das SK; Fujita S; Ho PH; Horiguchi S; Jiang X; Nakano K; Olariu S; Stojmenovic I; Wang H; Wu J; Xu CZ; Xue J; Zhou BB; Guo M; Zomaya AY, 2006, 'Special Section on Parallel/Distributed Computing and Networking', IEICE Transactions on Information and Systems, E89-D, pp. 387 - 388, http://dx.doi.org/10.1093/ietisy/e89-d.2.387

Xue J; Cai Q, 2006, 'A lifetime optimal algorithm for speculative PRE', ACM Transactions on Architecture and Code Optimization, 3, pp. 115 - 155

Xue J; Cai Q; Lin L, 2006, 'Partial dead code elimination on predicated code regions', Journal of Systems Architecture, 36, pp. 1655 - 1685

Xue J; Vera X, 2004, 'Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behaviour', IEEE Transactions on Computers, 53, pp. 547 - 566

Xue J, 2002, 'Eigenvectors-Based Parallelisation of Nested Loops with Affine Dependences', Parallel Algorithms and Applications, pp. 237 - 248

LENDERS P; XUE J, 2002, 'EIGENVECTORS-BASED PARALLELISATION OF NESTED LOOPS WITH AFFINE DEPENDENCES', Parallel Algorithms and Applications, 17, pp. 227 - 248, http://dx.doi.org/10.1080/01495730108941442

Xue J; Lenders P, 2002, 'Space-Time Equations for Non-Unimodular Mappings', International Journal of Computer Mathematics, 79, pp. 555 - 572, http://dx.doi.org/10.1080/00207160210953

Xue J, 2002, 'Time-Minimal Tiling When Rise Is Larger Than Zero', Parallel Computing, pp. 915 - 936

Tang P; Xue J, 2000, 'Generating efficient tiled code for distributed memory machines', Parallel Computing, 26, pp. 1369 - 1410, http://dx.doi.org/10.1016/S0167-8191(00)00040-5

Chen S; Xue J, 1999, 'Partitioning and Scheduling Loops on NOWs', Computer Communications, pp. 1017 - 1033

Xue J; Huang C-H, 1998, 'Reuse-Driven Tiling for Improving Data Locality', International Journal of Parallel Programming, 26, http://dx.doi.org/10.1023/A:1018734612524

Xue J, 1997, 'On tiling as a loop transformation', Parallel Processing Letters, 7, pp. 409 - 424, http://dx.doi.org/10.1142/S0129626497000401

Xue J, 1997, 'Communication-Minimal Tiling of Uniform Dependence Loops', Journal of Parallel and Distributed Computin, 42, pp. 42 - 59, http://dx.doi.org/10.1006/jpdc.1997.1310

Xue J, 1997, 'On Tiling as a Loop Transformation', Parallel Processing Letters, 07, pp. 409 - 424, http://dx.doi.org/10.1142/S0129626497000401

Xue J, 1997, 'Unimodular transformations of non-perfectly nested loops', Parallel Computing, 22, pp. 1621 - 1645, http://dx.doi.org/10.1016/S0167-8191(96)00063-4

Xue J, 1996, 'Generalising the unimodular approach to restructure imperfectly nested loops', Parallel Processing Letters, 6, pp. 401 - 414, http://dx.doi.org/10.1142/S0129626496000388

Xue J, 1996, 'GENERALISING THE UNIMODULAR APPROACH TO RESTRUCTURE IMPERFECTLY NESTED LOOPS', Parallel Processing Letters, 06, pp. 401 - 414, http://dx.doi.org/10.1142/S0129626496000388

Xue J, 1996, 'Transformations of nested loops with non-convex iteration spaces', Parallel Computing, 22, pp. 339 - 368, http://dx.doi.org/10.1016/0167-8191(95)00069-0

Xue J, 1995, 'Closed-form mapping conditions for the synthesis of linear processor arrays', Journal of VLSI signal processing systems for signal, image and video technology, 10, pp. 181 - 199, http://dx.doi.org/10.1007/BF02407035

Xue J, 1994, 'Automating non-unimodular loop transformations for massive parallelism', Parallel Computing, 20, pp. 711 - 728, http://dx.doi.org/10.1016/0167-8191(94)90002-7

Lengauer C; Xue J, 1992, 'A systolic array for pyramidal algorithms', Journal of VLSI Signal Processing, 4, pp. 89, http://dx.doi.org/10.1007/BF00930620

XUE JL, 1992, 'ON THE LOADING, RECOVERY AND ACCESS OF STATIONARY DATA IN SYSTOLIC ARRAYS', LECTURE NOTES IN COMPUTER SCIENCE, 634, pp. 259 - 264, https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:A1992KQ20400031&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=891bb5ab6ba270e68a29b250adbe88d1

Xue J; Lengauer C, 1992, 'The synthesis of control signals for one-dimensional systolic arrays', Integration, the VLSI Journal, 14, pp. 1 - 32, http://dx.doi.org/10.1016/0167-9260(92)90008-M

Lengauer C; Xue J, 1991, 'A systolic array for pyramidal algorithms', Journal of VLSI signal processing systems for signal, image and video technology, 3, pp. 237 - 257, http://dx.doi.org/10.1007/BF00925834

XUE JINGLING, 1991, 'SPECIFYING CONTROL SIGNALS FOR SYSTOLIC ARRAYS BY UNIFORM RECURRENCE EQUATIONS', Parallel Processing Letters, 01, pp. 83 - 93, http://dx.doi.org/10.1142/S0129626491000033

Xue J-L; Hong X-L, 1988, 'A new data structure for representing cell hierarchy in layout design', Computers & Graphics, 12, pp. 341 - 348, http://dx.doi.org/10.1016/0097-8493(88)90055-6

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