Select Publications
Books
2014, Functional Verification of Dynamically Reconfigurable FPGA-based Systems, Springer
,2000, 7th Reconfigurable Architectures Workshop (RAW2000)
,Book Chapters
2016, 'Overview and Investigation of SEU Detection and Recovery Approaches for FPGA-Based Heterogeneous Systems', in FPGAs and Parallel Architectures for Aerospace Applications Soft Errors and Fault-Tolerant Design, Springer, pp. 33 - 46, http://dx.doi.org/10.1007/978-3-319-14352-1_3
,Journal articles
2019, 'Efficient fine-grained processor-logic interactions on the cache-coherent zynq platform', ACM Transactions on Reconfigurable Technology and Systems, 11, http://dx.doi.org/10.1145/3277506
,2018, 'FMER: An Energy-Efficient Error Recovery Methodology for SRAM-Based FPGA Designs', IEEE Transactions on Aerospace and Electronic Systems, 54, pp. 2695 - 2712, http://dx.doi.org/10.1109/TAES.2018.2828201
,2018, 'Reconfiguration Control Networks for FPGA-based TMR systems with modular error recovery', Microprocessors and Microsystems, 60, pp. 86 - 95, http://dx.doi.org/10.1016/j.micpro.2018.04.006
,2018, 'Fine-grained module-based error recovery in FPGA-based TMR systems', ACM Transactions on Reconfigurable Technology and Systems, 11, pp. 1 - 23, http://dx.doi.org/10.1145/3173549
,2017, 'Fault recovery time analysis for coarse-grained reconfigurable architectures', ACM Transactions on Embedded Computing Systems, 17, pp. 1 - 21, http://dx.doi.org/10.1145/3140944
,2017, 'Service-Oriented Architecture on FPGA-Based MPSoC', IEEE Transactions on Parallel and Distributed Systems, 28, pp. 2993 - 3006, http://dx.doi.org/10.1109/TPDS.2017.2701828
,2017, 'The first 25 years of the FPL conference: Significant papers', ACM Transactions on Reconfigurable Technology and Systems, 10, http://dx.doi.org/10.1145/2996468
,2014, 'Simulation-based functional verification of dynamically reconfigurable systems', ACM Transactions on Embedded Computing Systems (TECS), 13, pp. 97 - 97
,2012, 'Guest editorial: Field-programmable technology', Journal of Signal Processing Systems, 67, pp. 1 - 2, http://dx.doi.org/10.1007/s11265-011-0653-3
,2010, 'Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration', ACM Transactions on Reconfigurable Technology and Systems, 3, pp. 1 - 36, http://dx.doi.org/10.1145/1661438.1661442
,2004, 'FPGA Implementation of Population-based Ant Colony Optimization', Applied soft computing : the official journal of the World Federation on Soft Computing (WFSC), 4, pp. 303 - 322
,2002, 'Towards high-level specification, synthesis, and virtualization of programmable logic designs', European Conference on Parallel Processing, pp. 314 - 317
,2001, 'A hardware compiler realizing concurrent processes in reconfigurable logic', IEE Proceedings-Computers and Digital Techniques, 148, pp. 152 - 162
,2001, 'On dynamic task scheduling for FPGA-based systems', International Journal of Foundations of Computer Science, 12, pp. 645 - 669
,2000, 'Dynamic scheduling of tasks on partially reconfigurable FPGAs', IEE Proceedings-Computers and Digital Techniques, 147, pp. 181 - 188
,1996, 'Optimal algorithms for constrained reconfigurable meshes', Journal of Parallel and Distributed Computing, 39, pp. 74 - 78
,Conference Papers
2022, 'Leveraging FPGA Runtime Reconfigurability to Implement Multi-Hash-Chain Proof-of-Work', in Proceedings - 2022 IEEE 30th International Symposium on Field-Programmable Custom Computing Machines, FCCM 2022, http://dx.doi.org/10.1109/FCCM53951.2022.9786081
,2022, 'On the Single Event Upset Vulnerability and Mitigation of Binarized Neural Networks on FPGAs', in Proceedings - 2022 IEEE 30th International Symposium on Field-Programmable Custom Computing Machines, FCCM 2022, http://dx.doi.org/10.1109/FCCM53951.2022.9786099
,2019, '2019 Reconfigurable Architectures Workshop', in Proceedings - 2019 IEEE 33rd International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2019, pp. 69, http://dx.doi.org/10.1109/IPDPSW.2019.00018
,2019, 'Scheduling configuration memory error checks to improve the reliability of FPGA-based systems', in IET Computers and Digital Techniques, pp. 198 - 205, http://dx.doi.org/10.1049/iet-cdt.2018.5001
,2018, 'A Short-Transfer Model for Tightly-Coupled CPU-FPGA Platforms', in Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018, pp. 369 - 372, http://dx.doi.org/10.1109/FPT.2018.00075
,2018, 'From C to Fault-Tolerant FPGA-Based Systems', in Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018, Institute of Electrical and Electronics Engineers (IEEE), CO, Boulder, pp. 212, presented at 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), CO, Boulder, 29 April 2018 - 01 May 2018, http://dx.doi.org/10.1109/FCCM.2018.00046
,2017, 'Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems', in 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017, Institute of Electrical and Electronics Engineers (IEEE), pp. 1 - 4, presented at 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 23 October 2017 - 25 October 2017, http://dx.doi.org/10.1109/DFT.2017.8244455
,2017, 'Scheduling Voter Checks to Detect Configuration Memory Errors in FPGA-based TMR Systems', in 2017 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT), IEEE, ENGLAND, Cambridge, pp. 131 - 134, presented at IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), ENGLAND, Cambridge, 23 October 2017 - 25 October 2017, https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000426958300028&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=891bb5ab6ba270e68a29b250adbe88d1
,2017, 'Reliable SEU monitoring and recovery using a programmable configuration controller', in 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Ghent, Belgium, presented at 2017 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, Belgium, 04 September 2017 - 08 September 2017, http://dx.doi.org/10.23919/FPL.2017.8056798
,2017, 'Scheduling considerations for voter checking in TMR-MER systems', in Proceedings - IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017, Institute of Electrical and Electronics Engineers (IEEE), Napa, CA, USA, pp. 30 - 30, presented at 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, USA, 30 April 2017 - 02 May 2017, http://dx.doi.org/10.1109/FCCM.2017.17
,2017, 'TLegUp: A TMR code generation tool for SRAM-based FPGA applications using HLS', in Proceedings - IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017, Institute of Electrical and Electronics Engineers (IEEE), CA, Napa, pp. 129 - 132, presented at 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), CA, Napa, 30 April 2017 - 02 May 2017, http://dx.doi.org/10.1109/FCCM.2017.57
,2016, 'Dynamic scheduling of voter checks in FPGA-based TMR systems', in Proceedings of the 2016 International Conference on Field-Programmable Technology, FPT 2016, Xi'an, China, pp. 169 - 172, presented at 2016 International Conference on Field-Programmable Technology (FPT), Xi'an, China, 07 December 2016 - 09 December 2016, http://dx.doi.org/10.1109/FPT.2016.7929525
,2016, 'Fine-grained Module-based Error Recovery in FPGA-based TMR Systems', in Song YC; Wang S; Nelson B; Li J; Peng Y (eds.), International Conference on Field-Programmable Technology (FPT), Institute of Electrical and Electronics Engineers (IEEE), Xi'an, China, pp. 101 - 108, presented at International Conference on Field-Programmable Technology, Xi'an, China, 07 December 2016 - 09 December 2016, http://dx.doi.org/10.1109/FPT.2016.7929433
,2016, 'A Programmable Configuration Controller for Fault-Tolerant Applications', in Song YC; Wang S; Nelson B; Li J; Peng Y (eds.), The 2016 International Conference on Field-Programmable Technology (FPT'16), Institute of Electrical and Electronics Engineers (IEEE), Xi'an, China, pp. 117 - 124, presented at The 2016 International Conference on Field-Programmable Technology (FPT'16), Xi'an, China, 07 December 2016 - 09 December 2016, http://dx.doi.org/10.1109/FPT.2016.7929515
,2016, 'Dynamic Scheduling of Voter Checks in FPGA-based TMR Systems', in The 2016 International Conference on Field-Programmable Technology (FPT'16), Xi'an, China, pp. M2 - M2, presented at The 2016 International Conference on Field-Programmable Technology (FPT'16), Xi'an, China, 07 December 2016 - 09 December 2016
,2016, 'FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs', in Field Programmable Logic and Applications (FPL), 2016 26th International Conference on, Institute of Electrical and Electronics Engineers (IEEE), EPFL, pp. 1 - 4, presented at 2016 26th International Conference on Field Programmable Logic and Applications (FPL), EPFL, 29 August 2016 - 02 September 2016, http://dx.doi.org/10.1109/FPL.2016.7577339
,2016, 'Reconfiguration Control Networks for TMR Systems with Module-based Recovery', in Proceedings - 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016, Institute of Electrical and Electronics Engineers (IEEE), USA, pp. 88 - 91, presented at IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), USA, 01 May 2016 - 03 May 2016, http://dx.doi.org/10.1109/FCCM.2016.30
,2015, 'Improving F max of FPGA circuits employing DPR to recover from configuration memory upsets', in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Institute of Electrical and Electronics Engineers (IEEE), IEEE, pp. 1190 - 1193, presented at 2015 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, 24 May 2015 - 27 May 2015, http://dx.doi.org/10.1109/ISCAS.2015.7168852
,2015, 'A programmable multi-gnss baseband receiver', in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, pp. 1178 - 1181, IEEE
,2015, 'Significant papers from the first 25 years of the FPL conference', in International Conference on Field Programmable Logic and Applications, IEEE, IEEE
,2015, 'Towards OS kernel acceleration in heterogeneous systems', in First International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC15), IEEE, IEEE
,2014, 'Reconfiguration network design for SEU recovery in FPGAs', in Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1524 - 1527, http://dx.doi.org/10.1109/ISCAS.2014.6865437
,2013, 'Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration', in 2013 23rd International Conference on Field Programmable Logic and Applications (FPL 2013), Porto, Portugal, pp. 1 - 4, presented at 2013 23rd International Conference on Field Programmable Logic and Applications (FPL), Porto, Portugal, 02 September 2013 - 04 September 2013, http://dx.doi.org/10.1109/FPL.2013.6645571
,2013, 'Opportunities and challenges for dynamic FPGA reconfiguration in electronic measurement and instrumentation', in Electronic Measurement & Instruments (ICEMI), 2013 IEEE 11th International Conference on, IEEE, pp. 258 - 263, IEEE
,2012, 'Functionally Verifying State Saving and Restoration in Dynamically Reconfigurable Systems', in ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA, Association for Computing Machinery, New York, NY, United States, pp. 241 - 244, presented at 2012 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA'12, Monterey, California, USA, 22 February 2012 - 24 February 2012, http://dx.doi.org/10.1145/2145694.2145735
,2011, 'Optimization of Placement of Dynamic Network-on-chip Cores Using Simulated Annealing', in IEEE, Proceedings of the 37th Annual Conference of the IEEE Industrial Electronics Society, Australia, pp. 2400 - 2405, presented at 37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011, Melbourne, VIC., Australia, 07 November 2011 - 10 November 2011, http://dx.doi.org/10.1109/IECON.2011.6119685
,2011, 'Modeling Dynamically Reconfigurable Systems for Simulation-based Functional Verification', in IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, New York, NY, United States, pp. 9 - 16, presented at IEEE International Symposium on Field-Programmable Custom Computing Machines, Salt Lake City, Utah, USA, 01 May 2011 - 03 May 2011, http://dx.doi.org/10.1109/FCCM.2011.18
,2011, 'Raw introduction', Institute of Electrical and Electronics Engineers (IEEE), pp. 125 - 127, presented at 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, http://dx.doi.org/10.1109/ipdps.2011.396
,2011, 'ReSim: A Reusable Library for RTL Simulation of Dynamic Partial Reconfiguration', in International Conference on Field Programmable Technology, IEEE Computer Society, New York, NY, United States, pp. 1 - 8, presented at International Conference on Field-Programmable Technology, New Delhi, India, http://dx.doi.org/10.1109/FPT.2011.6132709
,2010, 'FPGA-based video processing for a vision prosthesis', in Proceedings, 2010 International Conference on Field-Programmable Technology, IEEE, Beijing, China, pp. 345 - 348, presented at 2010 International Conference on Field-Programmable Technology, FPT 10, Beijing, China, 08 December 2010 - 10 December 2010, http://dx.doi.org/10.1109/FPT.2010.5681430
,2009, 'Message from the general chair and program co-chairs', in Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09, http://dx.doi.org/10.1109/FPT.2009.5377600
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