ORCID as entered in ROS
https://orcid.org/0000-0003-0725-5957
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Conference Papers
, 2022, 'Leveraging FPGA Runtime Reconfigurability to Implement Multi-Hash-Chain Proof-of-Work', in Proceedings - 2022 IEEE 30th International Symposium on Field-Programmable Custom Computing Machines, FCCM 2022, http://dx.doi.org/10.1109/FCCM53951.2022.9786081
, 2022, 'On the Single Event Upset Vulnerability and Mitigation of Binarized Neural Networks on FPGAs', in Proceedings - 2022 IEEE 30th International Symposium on Field-Programmable Custom Computing Machines, FCCM 2022, http://dx.doi.org/10.1109/FCCM53951.2022.9786099
, 2019, '2019 Reconfigurable Architectures Workshop', in Proceedings - 2019 IEEE 33rd International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2019, pp. 69, http://dx.doi.org/10.1109/IPDPSW.2019.00018
, 2019, 'Scheduling configuration memory error checks to improve the reliability of FPGA-based systems', in IET Computers and Digital Techniques, pp. 198 - 205, http://dx.doi.org/10.1049/iet-cdt.2018.5001
, 2018, 'A Short-Transfer Model for Tightly-Coupled CPU-FPGA Platforms', in Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018, pp. 369 - 372, http://dx.doi.org/10.1109/FPT.2018.00075
, 2018, 'From C to Fault-Tolerant FPGA-Based Systems', in Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018, Institute of Electrical and Electronics Engineers (IEEE), CO, Boulder, pp. 212, presented at
, 2017, 'Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems', in 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017, Institute of Electrical and Electronics Engineers (IEEE), pp. 1 - 4, presented at
, 2017, 'Scheduling Voter Checks to Detect Configuration Memory Errors in FPGA-based TMR Systems', in 2017 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT), IEEE, ENGLAND, Cambridge, pp. 131 - 134, presented at
, 2017, 'Reliable SEU monitoring and recovery using a programmable configuration controller', in 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Ghent, Belgium, presented at
, 2017, 'Scheduling considerations for voter checking in TMR-MER systems', in Proceedings - IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017, Institute of Electrical and Electronics Engineers (IEEE), Napa, CA, USA, pp. 30 - 30, presented at
, 2017, 'TLegUp: A TMR code generation tool for SRAM-based FPGA applications using HLS', in Proceedings - IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017, Institute of Electrical and Electronics Engineers (IEEE), CA, Napa, pp. 129 - 132, presented at
, 2016, 'Dynamic scheduling of voter checks in FPGA-based TMR systems', in Proceedings of the 2016 International Conference on Field-Programmable Technology, FPT 2016, Xi'an, China, pp. 169 - 172, presented at
, 2016, 'Fine-grained Module-based Error Recovery in FPGA-based TMR Systems', in Song YC; Wang S; Nelson B; Li J; Peng Y (eds.), International Conference on Field-Programmable Technology (FPT), Institute of Electrical and Electronics Engineers (IEEE), Xi'an, China, pp. 101 - 108, presented at
, 2016, 'A Programmable Configuration Controller for Fault-Tolerant Applications', in Song YC; Wang S; Nelson B; Li J; Peng Y (eds.), The 2016 International Conference on Field-Programmable Technology (FPT'16), Institute of Electrical and Electronics Engineers (IEEE), Xi'an, China, pp. 117 - 124, presented at
, 2016, 'Dynamic Scheduling of Voter Checks in FPGA-based TMR Systems', in The 2016 International Conference on Field-Programmable Technology (FPT'16), Xi'an, China, pp. M2 - M2, presented at
, 2016, 'FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs', in Field Programmable Logic and Applications (FPL), 2016 26th International Conference on, Institute of Electrical and Electronics Engineers (IEEE), EPFL, pp. 1 - 4, presented at
, 2016, 'Reconfiguration Control Networks for TMR Systems with Module-based Recovery', in Proceedings - 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016, Institute of Electrical and Electronics Engineers (IEEE), USA, pp. 88 - 91, presented at
, 2015, 'Improving F max of FPGA circuits employing DPR to recover from configuration memory upsets', in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Institute of Electrical and Electronics Engineers (IEEE), IEEE, pp. 1190 - 1193, presented at
, 2015, 'A programmable multi-gnss baseband receiver', in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, pp. 1178 - 1181, IEEE
, 2015, 'Significant papers from the first 25 years of the FPL conference', in International Conference on Field Programmable Logic and Applications, IEEE, IEEE
, 2015, 'Towards OS kernel acceleration in heterogeneous systems', in First International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC15), IEEE, IEEE
, 2014, 'Reconfiguration network design for SEU recovery in FPGAs', in Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1524 - 1527, http://dx.doi.org/10.1109/ISCAS.2014.6865437
, 2013, 'Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration', in 2013 23rd International Conference on Field Programmable Logic and Applications (FPL 2013), Porto, Portugal, pp. 1 - 4, presented at
, 2013, 'Opportunities and challenges for dynamic FPGA reconfiguration in electronic measurement and instrumentation', in Electronic Measurement & Instruments (ICEMI), 2013 IEEE 11th International Conference on, IEEE, pp. 258 - 263, IEEE
, 2012, 'Functionally Verifying State Saving and Restoration in Dynamically Reconfigurable Systems', in ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA, Association for Computing Machinery, New York, NY, United States, pp. 241 - 244, presented at
, 2011, 'Optimization of Placement of Dynamic Network-on-chip Cores Using Simulated Annealing', in IEEE, Proceedings of the 37th Annual Conference of the IEEE Industrial Electronics Society, Australia, pp. 2400 - 2405, presented at
, 2011, 'Modeling Dynamically Reconfigurable Systems for Simulation-based Functional Verification', in IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, New York, NY, United States, pp. 9 - 16, presented at
, 2011, 'Raw introduction', Institute of Electrical and Electronics Engineers (IEEE), pp. 125 - 127, presented at
, 2011, 'ReSim: A Reusable Library for RTL Simulation of Dynamic Partial Reconfiguration', in International Conference on Field Programmable Technology, IEEE Computer Society, New York, NY, United States, pp. 1 - 8, presented at
, 2010, 'FPGA-based video processing for a vision prosthesis', in Proceedings, 2010 International Conference on Field-Programmable Technology, IEEE, Beijing, China, pp. 345 - 348, presented at
, 2009, 'Message from the general chair and program co-chairs', in Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09, http://dx.doi.org/10.1109/FPT.2009.5377600
, 2008, 'ACS: an addressless configuration support for efficient partial reconfigurations', in International conference on field-programmable technology, Proceedings, Taipei, Taiwan, pp. 161 - 168, presented at
, 2008, 'The effectiveness of configuration merging in point-to-point networks for module-based FPGA reconfiguration', in Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM'08, pp. 65 - 76, http://dx.doi.org/10.1109/FCCM.2008.25
, 2008, 'The effectiveness of configuration merging in point-to-point networks', in IEEE symposium on field-programmable custom computing machines 2008, Stanford, California, USA, presented at
, 2007, 'Fast code-phase alignment of GPS signals using Virtex-4 FPGAs', in IGNSS 2007, UNSW, Sydney, Australia, presented at
, 2007, 'Module graph merging and placement to reduce reconfiguration overheads in paged FPGA devices', in International Conference on Field Programmable Logic 2007, Amsterdam, Netherlands, presented at
, 2006, 'Communications Infrastructure Generation for Modular FPGA Reconfiguration', in IEEE International Conference in Field Programmable Technology, Bangkok, Thailand, presented at
, 2006, 'The entropy of FPGA reconfiguration', in Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL, pp. 261 - 266, http://dx.doi.org/10.1109/FPL.2006.311223
, 2006, 'Functional unit chaining: a runtime adaptive architecture for reducing bypass delays', in Advances in computer systems architecture, 11th Asia-Pacific conference, Shanghai, China, presented at
, 2006, 'The enotropy of FPGA reconfiguration', in 2006 International Conference on Field Programming, Madrid, Spain, presented at
, 2006, 'COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs', in IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, New York, NY, United States, presented at
, 2006, 'COMMA: a communications methodology for dynamic module-based reconfiguration of FPGAs', in 19th international conference on architecture of computing systems, Frankfurt, Germany, presented at
, 2006, 'Enabling RTR for industry', in Dagstuhl Seminar Proceedings, Schloss Dagstuhl-Leibniz-Zentrum für Informatik, Schloss Dagstuhl-Leibniz-Zentrum für Informatik
, 2006, 'The entropy of FPGA reconfiguration', in 2006 International Conference on Field Programmable Logic and Applications, IEEE, pp. 1 - 6, IEEE
, 2005, 'A configuration system architecture supporting bit-stream compression for FPGAs', in 10th Asia-Pacific conference on computer systems architecture, Singapore, presented at
, 2005, 'A configuration memory architecture for fast run-time reconfiguration of FPGAs', in 2005 International conference on field programmable logic (FPL 2005), Finland, presented at
, 2004, 'Message from the general chair and program chair', in Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04
, 2004, 'On the placement and granularity of FPGA configurations', in Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on, IEEE, pp. 161 - 168, IEEE
, 2002, 'Towards High-Level Specification, Synthesis, and Virtualization of Programmable Logic Designs', in Monien B; Feldmann R (ed.), Euro-Par 2002, Paderborn Germany, pp. 314 - 317, presented at
, 2002, 'An FPGA interpreter with virtual hardware management', in International Parallel Processing Symposium, Springer, Springer
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https://orcid.org/0000-0003-0725-5957