By Professor Sri Parameswaran

Conference Papers

Liyanage K; Gamaarachchi H; Saadat H; Li T; Samarakoon H; Parameswaran S, 2024, 'Accelerating Chaining in Genomic Analysis Using RISC- V Custom Instructions', in Proceedings -Design, Automation and Test in Europe, DATE

Bhargavi MB; Siddharth Rokkam S; Parameswaran S; Soumya J, 2024, 'Automated Design and Configuration of RISC-V based NoC-MPSoC Framework on FPGA', in 2024 28th International Symposium on VLSI Design and Test, VDAT 2024, http://dx.doi.org/10.1109/VDAT63601.2024.10705744

Bhargavi MB; Sai Harshith GS; Parameswaran S; Soumya J, 2024, 'Optimizing LU Decomposition with RISC-V Based Hardware Acceleration', in Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, pp. 210 - 215, http://dx.doi.org/10.1109/ISVLSI61997.2024.00047

Gong J; Saadat H; Javaid H; Gamaarachchi H; Taubman D; Parameswaran S, 2024, 'SEA: Sign-Separated Accumulation Scheme for Resource-Efficient DNN Accelerators', in Proceedings -Design, Automation and Test in Europe, DATE

Udugama B; Jayasinghe D; Parameswaran S, 2024, 'Sensors for Remote Power Attacks: New Developments and Challenges', in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 333 - 340, http://dx.doi.org/10.1109/ASP-DAC58780.2024.10473890

Jayasinghe D; Udugama B; Parameswaran S, 2023, 'FPGA Based Countermeasures against Side Channel Attacks on Block Ciphers', in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 365 - 371, http://dx.doi.org/10.1145/3566097.3568353

Gamaarachchi H; Liyanage K; Parameswaran S, 2023, 'Invited: Algorithms and Architectures for Accelerating Long Read Sequence Analysis', in Proceedings - Design Automation Conference, http://dx.doi.org/10.1109/DAC56929.2023.10247772

Li T; Parameswaran S, 2022, 'FaSe: Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks', in Proceedings - Design Automation Conference, pp. 541 - 546, http://dx.doi.org/10.1145/3489517.3530491

Dow HK; Li T; Parameswaran S, 2022, 'HWST128: Complete Memory Safety Accelerator on RISC-V with Metadata Compression', in Proceedings - Design Automation Conference, pp. 709 - 714, http://dx.doi.org/10.1145/3489517.3530548

Dow HK; Li T; Miles W; Parameswaran S, 2021, 'SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V', in Proceedings - Design Automation Conference, pp. 289 - 294, http://dx.doi.org/10.1109/DAC18074.2021.9586293

Zervakis G; Saadat H; Mrouch H; Gerstlauer A; Parameswaran S; Henkel J, 2021, 'Approximate Computing for ML: State-of-the-art, Challenges and Visions', in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 189 - 196, http://dx.doi.org/10.1145/3394885.3431632

Laguna AF; Gamaarachchi H; Yin X; Niemier M; Parameswaran S; Hu XS, 2020, 'Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping', in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, http://dx.doi.org/10.1145/3400302.3415651

Gnanasambandapillai V; Peddersen J; Ragel R; Parameswaran S, 2020, 'FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications', in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 3577 - 3588, http://dx.doi.org/10.1109/TCAD.2020.3012211

Abid F; Jayasinghe D; Somsavaddy S; Parameswaran S, 2020, 'LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs', in Proceedings - 30th International Conference on Field-Programmable Logic and Applications, FPL 2020, pp. 162 - 168, http://dx.doi.org/10.1109/FPL50879.2020.00036

Saadat H; Javaid H; Ignjatovic A; Parameswaran S, 2020, 'REALM: Reduced-Error Approximate Log-based Integer Multiplier', in Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020, pp. 1366 - 1371, http://dx.doi.org/10.23919/DATE48585.2020.9116315

Saadat H; Javaid H; Ignjatovic A; Parameswaran S, 2020, 'WEID: Worst-case Error Improvement in Approximate Dividers', in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Institute of Electrical and Electronics Engineers (IEEE), PEOPLES R CHINA, Beijing, pp. 593 - 598, presented at 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), PEOPLES R CHINA, Beijing, 13 January 2020 - 16 January 2020, http://dx.doi.org/10.1109/ASP-DAC47756.2020.9045504

Saadat H; Li T; Javaid H; Parameswaran S, 2020, 'A sub-range error characterization based selection methodology for approximate arithmetic units', in Proceedings - 33rd International Conference on VLSI Design, VLSID 2020 - Held concurrently with 19th International Conference on Embedded Systems, pp. 84 - 89, http://dx.doi.org/10.1109/VLSID49098.2020.00032

Jayasinghe D; Ignjatovic A; Parameswaran S, 2019, 'SCRIP: Secure random clock execution on soft processor systems to mitigate power-based side channel attacks', in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, http://dx.doi.org/10.1109/ICCAD45719.2019.8942112

Prasad Mohanty R; Gamaarachchi H; Lambert A; Parameswaran S, 2019, 'Swaram: Portable energy and cost efficient embedded system for genomic processing', in ACM Transactions on Embedded Computing Systems, http://dx.doi.org/10.1145/3358211

Saadat H; Javaid H; Parameswaran S, 2019, 'Approximate integer and floating-point dividers with near-zero error bias', in Proceedings - Design Automation Conference, http://dx.doi.org/10.1145/3316781.3317773

Jayasinghe D; Ignjatovic A; Parameswaran S, 2019, 'RFTC: Runtime frequency tuning countermeasure using FPGA dynamic reconfiguration to mitigate power analysis attacks', in Proceedings - Design Automation Conference, http://dx.doi.org/10.1145/3316781.3317899

Malekpour A; Ragel R; Murphy D; Ignjatovic A; Parameswaran S, 2019, 'Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing', in Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019, http://dx.doi.org/10.1109/DDECS.2019.8724649

Hussain M; Malekpour A; Guo H; Parameswaran S, 2018, 'EETD: An energy efficient design for runtime hardware trojan detection in untrusted network-on-chip', in Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, pp. 345 - 350, http://dx.doi.org/10.1109/ISVLSI.2018.00070

Parameswaran S; Kishore R, 2018, 'Social support in online health communities: A social-network approach', in SIGMIS-CPR 2018 - Proceedings of the 2018 ACM SIGMIS Conference on Computers and People Research, pp. 93 - 94, http://dx.doi.org/10.1145/3209626.3209725

Irena F; Murphy D; Parameswaran S, 2018, 'CryptoBlaze: A partially homomorphic processor with multiple instructions and non-deterministic encryption support', in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 702 - 708, http://dx.doi.org/10.1109/ASPDAC.2018.8297404

Gnanasambandapillai V; Bayat A; Parameswaran S, 2018, 'MESGA: An MPSoC based embedded system solution for short read genome alignment', in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 52 - 57, http://dx.doi.org/10.1109/ASPDAC.2018.8297282

Wang X; Bagul DM; Parameswaran S; Kishore R, 2018, 'Does Online Social Support Work in Stigmatized Chronic Diseases? A Study of the Impacts of Different Facets of Informational and Emotional Support on Self-Care Behavior in an HIV Online Forum', in ICIS 2017: Transforming Society with Digital Innovation

Saadat H; Parameswaran S, 2017, 'Special session: Hardware approximate computing: How, why, when and where?', in Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion, CASES 2017, Seoul, Republic of Korea, presented at 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion, Seoul, Republic of Korea, 15 October 2017 - 20 October 2017, http://dx.doi.org/10.1145/3125501.3125518

Malekpour A; Ragel R; Ignjatovic A; Parameswaran S, 2017, 'DoSGuard: Protecting pipelined MPSoCs against hardware Trojan based DoS attacks', in Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, Seattle, WA, USA, pp. 45 - 52, presented at 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Seattle, WA, USA, 10 July 2017 - 12 July 2017, http://dx.doi.org/10.1109/ASAP.2017.7995258

Parameswaran S, 2017, 'Social presence in social media: Persuasion, design and discourse', in SIGMIS-CPR 2017 - Proceedings of the 2017 ACM SIGMIS Conference on Computers and People Research, pp. 205 - 206, http://dx.doi.org/10.1145/3084381.3084428

Khinda R; Parameswaran S; Mitra G; Lin X; Verni C; Kishore R; Billittier A, 2017, 'Use of gamified social media with home telemonitoring for patient self-management in poorly controlled medicaid diabetics: A pilot study of health outcomes, social influences, and habit formation', in SIGMIS-CPR 2017 - Proceedings of the 2017 ACM SIGMIS Conference on Computers and People Research, pp. 171 - 172, http://dx.doi.org/10.1145/3084381.3084417

Malekpour A; Ragel R; Ignjatovic A; Parameswaran S, 2017, 'TrojanGuard: Simple and Effective Hardware Trojan Mitigation Techniques for Pipelined MPSoCs', in Proceedings - Design Automation Conference, http://dx.doi.org/10.1145/3061639.3062336

Ignjatovic A; Jayasinghe D; Parameswaran S, 2017, 'NORA: Algorithmic Balancing without Pre-charge to Thwart Power Analysis Attacks', in VLSI Design 2017, Hyderabad, India, presented at 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, VLSID 2017, Hyderabad, India, 07 January 2017 - 11 January 2017

Parameswaran S; Kishore R, 2017, 'A social presence model of task performance: A meta-analytic structural equation model', in AMCIS 2017 - America's Conference on Information Systems: A Tradition of Innovation

Nemati N; Reed MC; Parameswaran S; Fant K, 2016, 'Self-Timed automatic test pattern generation for null convention logic', in Midwest Symposium on Circuits and Systems, Abu Dhabi, United Arab Emirates, presented at 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi, United Arab Emirates, 16 October 2016 - 19 October 2016, http://dx.doi.org/10.1109/MWSCAS.2016.7870032

Nemati N; Reed MC; Parameswaran S; Fant K, 2016, 'Self-Timed Automatic Test Pattern Generation for Null Convention Logic', in 2016 IEEE 59TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), IEEE, U ARAB EMIRATES, Abu Dhabi, pp. 369 - 372, presented at 59th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), U ARAB EMIRATES, Abu Dhabi, 16 October 2016 - 19 October 2016

Aluthwala P; Weste N; Adams A; Lehmann T; Parameswaran S, 2016, 'The effect of amplitude resolution and mismatch on a digital-to-analog converter used for digital harmonic-cancelling sine-wave synthesis', in Proceedings - IEEE International Symposium on Circuits and Systems, IEEE, Montreal, CANADA, pp. 2018 - 2021, presented at IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, CANADA, 22 May 2016 - 25 May 2016, http://dx.doi.org/10.1109/ISCAS.2016.7538973

Jayasinghe JA; Shivam Bashin ; Parameswaran S; Ignjatovic A, 2016, 'Does It Sound as It Claims: A Detailed Side-Channel Security Analysis of QuadSeal Countermeasure', Como, Italy, presented at ACM International Conference on Computing Frontiers 2016, Como, Italy, 16 May 2016 - 18 May 2016, http://dx.doi.org/10.1145/2903150.2911709

Li T; Ambrose JA; Parameswaran S, 2016, 'RECORD: Reducing register traffic for checkpointing in embedded processors', in Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, pp. 582 - 587, http://dx.doi.org/10.3850/9783981537079_0191

Liu T; Guo H; Parameswaran S; Hu XS, 2016, 'Improving tag generation for memory data authentication in embedded processor systems', in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 50 - 55, http://dx.doi.org/10.1109/ASPDAC.2016.7427988

Jayasinghe D; Ignjatovic A; Ambrose JA; Ragel R; Parameswaran S, 2015, 'QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks', in 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015, pp. 21 - 30, http://dx.doi.org/10.1109/CASES.2015.7324539

Shwe S; Batra K; Yachide Y; Peddersen JM; Parameswaran S, 2015, 'RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory', in Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015, Institute of Electrical and Electronics Engineers (IEEE), New York, NY, USA, pp. 635 - 642, presented at IEEE International Conference on Computer Design (ICCD), New York, NY, USA, 18 October 2015 - 21 October 2015, http://dx.doi.org/10.1109/ICCD.2015.7357175

Ambrose JA; Yachide Y; Batra K; Peddersen JMD; Parameswaran S, 2015, 'Sequential C-code to Distributed Pipelined Heterogeneous MPSoC Synthesis for Streaming Applications', in Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015, Institute of Electrical and Electronics Engineers (IEEE), New York, NY, USA, pp. 216 - 223, presented at IEEE International Conference on Computer Design (ICCD), New York, NY, USA, 18 October 2015 - 21 October 2015, http://dx.doi.org/10.1109/ICCD.2015.7357106

Bokhari H; Parameswaran SRI; Shafique M; Garg S; Khan MUK; Khdr H; Kriebel F; Ogras UY; Henkel J, 2015, 'Dark Silicon: From Computation to Communication', Vancouver, Canada, presented at 9th International Symposium on Networks-on-Chip (NoC'15), Vancouver, Canada, 28 September 2015 - 30 September 2015, http://dx.doi.org/10.1145/2786572.2788707

Ambrose JA; Higgins N; Chakravarthy M; Garg S; Li T; Murphy D; Ignjatovic A; Parameswaran S, 2015, 'ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip', in Proceedings - IEEE International Symposium on Circuits and Systems, pp. 413 - 416, http://dx.doi.org/10.1109/ISCAS.2015.7168658

Bokhari H; Javaid H; Shafique M; Henkel J; Parameswaran S, 2015, 'SuperNet: Multimode interconnect architecture for manycore chIPs', in Proceedings - Design Automation Conference, http://dx.doi.org/10.1145/2744769.2744912

Aluthwala PD; Lehmann T; Parameswaran S, 2015, 'Design of a Digital Harmonic-Cancelling Sine-Wave Synthesizer with 100 MHz Output Frequency, 43.5 dB SFDR, and 2.26 mW Power', in Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers, Lisbon, Portugal, presented at International Symposium on Circuits and Systems, Lisbon, Portugal, 24 May 2015 - 27 May 2015

Tang L; Ambrose JA; Kumar A; Parameswaran S, 2015, 'Dynamic reconfigurable puncturing for secure wireless communication', in Proceedings -Design, Automation and Test in Europe, DATE, pp. 888 - 891, http://dx.doi.org/10.7873/date.2015.0851

Bokhari H; Javaid H; Shafique M; Henkel J; Parameswaran S, 2015, 'Malleable NoC: Dark silicon inspired adaptable Network-on-Chip', in Proceedings -Design, Automation and Test in Europe, DATE, pp. 1245 - 1248, http://dx.doi.org/10.7873/date.2015.0694

Ambrose JA; Ragel RG; Jayasinghe D; Li T; Parameswaran S, 2015, 'Side channel attacks in embedded systems: A tale of hostilities and deterrence', in Proceedings - International Symposium on Quality Electronic Design, ISQED, pp. 452 - 459, http://dx.doi.org/10.1109/ISQED.2015.7085468

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