Select Publications

Journal articles

Gamaarachchi H; Parameswaran S; Smith MA, 2019, 'Featherweight long read alignment using partitioned reference indexes', Scientific Reports, vol. 9, http://dx.doi.org/10.1038/s41598-019-40739-8

Gamaarachchi H; Parameswaran S; Smith M, 2018, 'Featherweight long read alignment using partitioned reference indexes', BIORXIV, http://dx.doi.org/10.1101/386847

Gamaarachchi H; Bayat A; Gaeta B; Parameswaran S, 2018, 'Cache Friendly Optimisation of de Bruijn Graph based Local Re-assembly in Variant Calling', IEEE/ACM Transactions on Computational Biology and Bioinformatics, http://dx.doi.org/10.1109/TCBB.2018.2881975

Saadat H; Bokhari H; Parameswaran S, 2018, 'Minimally biased multipliers for approximate integer and floating-point multiplication', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, pp. 2623 - 2635, http://dx.doi.org/10.1109/TCAD.2018.2857262

Bayat A; Deshpande NP; Wilkins MR; Parameswaran S, 2018, 'Fast Short Read De-novo Assembly Using Overlap-Layout-Consensus Approach', IEEE/ACM Transactions on Computational Biology and Bioinformatics, http://dx.doi.org/10.1109/TCBB.2018.2875479

Parameswaran S; Iris Bahar R; Pan DZ, 2018, 'Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD)', IEEE Design and Test, vol. 35, pp. 101 - 102, http://dx.doi.org/10.1109/MDAT.2018.2799991

Bayat A; Gaëta B; Ignjatovic A; Parameswaran S, 2017, 'Improved VCF normalization for accurate VCF comparison.', Bioinformatics, vol. 33, pp. 964 - 970, http://dx.doi.org/10.1093/bioinformatics/btw748

Aluthwala PD; Weste N; Adams A; Lehmann T; Parameswaran S, 2017, 'Partial dynamic element matching technique for digital-to-analog converters used for digital harmonic-cancelling sine-wave synthesis', IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, pp. 296 - 309, http://dx.doi.org/10.1109/TCSI.2016.2613938

Liu T; Guo H; Parameswaran S; Hu SX, 2017, 'iCETD: An improved tag generation design for memory data authentication in embedded processor systems', Integration, the VLSI Journal, vol. 56, pp. 96 - 104, http://dx.doi.org/10.1016/j.vlsi.2016.10.006

Li T; Shafique M; Ambrose JA; Henkel J; Parameswaran S, 2017, 'Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors', IEEE Transactions on Computers, vol. 66, pp. 647 - 660, http://dx.doi.org/10.1109/TC.2016.2606378

Li T; Ambrose JA; Ragel R; Parameswaran S, 2016, 'Processor design for soft errors: Challenges and state of the art', ACM Computing Surveys, vol. 49, http://dx.doi.org/10.1145/2996357

Nawinne I; Javaid H; Ragel R; Parameswaran S, 2016, 'Switchable cache: Utilising dark silicon for application specific cache optimisations', IET Computers and Digital Techniques, vol. 10, pp. 157 - 164, http://dx.doi.org/10.1049/iet-cdt.2015.0114

Parameswaran S, 2016, 'Editorial Introduction of New Editor-in-Chief and Associate Editors', IEEE Embedded Systems Letters, vol. 8, pp. 1, http://dx.doi.org/10.1109/LES.2016.2532418

Nawinne I; Javaid H; Ragel R; Radhakrishnan S; Parameswaran S, 2015, 'Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, pp. 1991 - 2003, http://dx.doi.org/10.1109/TCAD.2015.2445736

Javaid H; Ignjatovic A; Parameswaran S, 2014, 'Performance estimation of pipelined multiprocessor system-on-chips (MPSoCs)', IEEE Transactions on Parallel and Distributed Systems, vol. 25, pp. 2159 - 2168, http://dx.doi.org/10.1109/TPDS.2013.268

Javaid H; Shafique M; Henkel J; Parameswaran S, 2014, 'Energy-efficient adaptive pipelined MPSoCs for multimedia applications', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, pp. 663 - 676, http://dx.doi.org/10.1109/TCAD.2014.2298196

Ambrose JA; Ragel RG; Parameswaran S, 2012, 'Randomized Instruction Injection to Counter Power Analysis Attacks', ACM Transactions on Embedded Computing Systems (TECS), vol. 11, pp. 28, http://dx.doi.org/10.1145/2345770.2345782

Ambrose JA; Aldon N; Ignjatovic A; Parameswaran S, 2012, 'Differential Power Analysis in AES: A Crypto Anatomy', IJEI: International Journal of Engineering and Industries, vol. 2, pp. 118 - 130, http://www.aicit.org/ijei/global/paper_detail.html?jname=IJEI&q=46

Ambrose JA; Ragel RG; Parameswaran S; Ignjatovic A, 2011, 'Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks', IET Computers and Digital Techniques, vol. 5, pp. 1 - 15, http://dx.doi.org/10.1049/iet-cdt.2009.0097

Ragel RG; Parameswaran S, 2011, 'A hybrid hardware-software technique to improve reliability in embedded processors', ACM Transactions on Embedded Computing Systems (TECS), vol. 10, pp. Article number: 36, http://dx.doi.org/10.1145/1952522.1952529

Patel K; Parameswaran S; Ragel RG, 2011, 'Architectural frameworks for security and reliability of MPSoCs', IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, vol. 19, pp. 1641 - 1654, http://dx.doi.org/10.1109/TVLSI.2010.2053856

Henkel J; Parameswaran S, 2010, 'CASES 2009 guest editor's introduction', Design Automation for Embedded Systems, vol. 14, pp. 285 - 286, http://dx.doi.org/10.1007/s10617-010-9060-4

Javaid H; Ignjatovic A; Parameswaran S, 2010, 'Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, pp. 1777 - 1789, http://dx.doi.org/10.1109/TCAD.2010.2061353

Javaid H; He X; Ignjatovic A; Parameswaran S, 2010, 'Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications', 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010, pp. 75 - 84

Chong YJ; Parameswaran S, 2009, 'Custom floating-point unit generation for embedded systems', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, pp. 638 - 650

Avnit K; D'Silva V; Sowmya A; Ramesh S; Parameswaran S, 2009, 'Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis', ACM Transactions on Design Automation of Electronic Systems, vol. 14, http://dx.doi.org/10.1145/1497561.1497562

Chong Y; Parameswaran S, 2009, 'Custom Floating-Point Unit Generation for Embedded Systems', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, pp. 638 - 650, http://dx.doi.org/10.1109/TCAD.2009.2013999

Radhakrishnan S; Guo H; Parameswaran S; Ignjatovic A, 2009, 'HMP-ASIPs: Heterogeneous multi-pipeline application-specific instruction-set processors', IET Computers and Digital Techniques, vol. 3, pp. 94 - 108, http://dx.doi.org/10.1049/iet-cdt:20080005

Peddersen JM; Parameswaran S, 2008, 'Low-impact processor for dynamic runtime power management', IEEE Design and Test of Computers, vol. 25, pp. 52 - 62, http://dx.doi.org/10.1109/MDT.2008.23

Shee SL; Erdos A; Parameswaran S, 2008, 'Architectural exploration of heterogeneous multiprocessor systems for JPEG', International Journal of Parallel Programming, vol. 36, pp. 140 - 162, http://dx.doi.org/10.1007/s10766-007-0040-7

Peddersen JM; Parameswaran S, 2008, 'Energy driven application self-adaptation at run-time', Journal of Computers (JCP), vol. 3, pp. 14 - 24, http://dx.doi.org/10.4304/jcp.3.3.14-24

Parameswaran S; Wolf T, 2008, 'Embedded systems security - an overview', Design Automation for Embedded Systems, vol. 12, pp. 173 - 183, http://dx.doi.org/10.1007/s10617-008-9027-x

Wolf T; Parameswaran S, 2008, 'Guest editorial for special issue on embedded system security', Design Automation for Embedded Systems, vol. 12, pp. 171 - 172, http://dx.doi.org/10.1007/s10617-008-9029-8

Parameswaran S; Henkel J; Cheung N, 2007, 'Instruction matching and modeling', Customizable Embedded Processors, pp. 257 - 280, http://dx.doi.org/10.1016/B978-012369526-0/50012-7

Lu ISC, 2007, 'A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider', IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, pp. 323 - 327, http://dx.doi.org/10.1109/TCSII.2006.889741

Janapsatya A; Ignjatovic A; Parameswaran S, 2006, 'Exploiting statistical information for implementation of instruction scratchpad memory in embedded system', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, pp. 816 - 829, http://dx.doi.org/10.1109/TVLSI.2006.878470

Parameswaran S; Henkel J, 2005, 'Instruction code mapping for performance increase and energy reduction in embedded computer systems', IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, vol. 13, pp. 498 - 502, http://dx.doi.org/10.1109/TVLSI.2004.842936

Janapsatya AG; Henkel J; Parameswaran S, 2004, 'REMcode: relocating embedded code for improving system efficiency', IEE Proceedings-Computers and Digital Techniques, vol. 151, pp. 457 - 465, http://dx.doi.org/10.1049/ip-cdt:20040942

Parameswaran S; Henkel J, 2001, 'I-CoPES: Fast instruction code placement for embedded systems to improve performance and energy efficiency', IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, pp. 635 - 641, http://dx.doi.org/10.1109/ICCAD.2001.968728

Parameswaran S; Guo H, 1998, 'Power reduction in pipelines', Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 545 - 550

Ragel RG; Ambrose JA; Parameswaran S, 'SecureD: A Secure Dual Core Embedded Processor', SecureD: A Secure Dual Core Embedded Processor, http://arxiv.org/abs/1511.01946v1


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