By Professor Sri Parameswaran

Conference Papers

Zhang X; Haris J; Muhammad S; Jude Angelo A; Jörg H; Sri P, 2015, 'ADAPT: An ADAptive Manycore Methodology for Software Pipelined ApplicaTions', in ASP-DAC (ed.), presented at 20th Asia and South Pacific Design Automation Conference, 19 January 2015 - 22 January 2015

Schneider JL; Pedersen J; Parameswaran S, 2015, 'Speeding Up Single Pass Simulation of PLRUt Caches', presented at 2015 20th Asia and South Pacific Design Automation Conference, 19 January 2015 - 22 January 2015

Tang X; Kishore R; Parameswaran S, 2015, 'Dig deeper or diversify? The rewards and penalties of knowledge exploration and exploitation capabilities in the context of IS scholar publication productivity', in 2015 International Conference on Information Systems: Exploring the Information Frontier, ICIS 2015

Parameswaran S, 2014, 'Mapping programs for execution on pipelined MPSoCs', in 2014 IEEE 12th Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2014, pp. 11, http://dx.doi.org/10.1109/ESTIMedia.2014.6962340

Tang L; Ambrose JA; Parameswaran S; Zhu S, 2014, 'Reconfigurable convolutional codec for physical layer communication security application', in Proceedings - IEEE Military Communications Conference MILCOM, pp. 82 - 87, http://dx.doi.org/10.1109/MILCOM.2014.21

Jayasinghe D; Ragel R; Ambrose JA; Ignjatovic A; Parameswaram S, 2014, 'Advanced Modes in AES: Are they Safe from Power Analysis based Side Channel Attacks?', Seoul, Korea, presented at IEEE International Conference on Computer Design, Seoul, Korea, 19 October 2014 - 22 October 2014

Shafique M; Garg S; Mitra T; Parameswaran S; Henkel J, 2014, 'Dark silicon as a challenge for hardware/software co-design', in 2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2014, http://dx.doi.org/10.1145/2656075.2661645

Schneider JL; Peddersen J; Parameswaran S, 2014, 'MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis', in Proceedings of the The 51st Annual Design Automation Conference, ACM New York, NY, USA, San Francisco, California, USA, pp. 1 - 6, presented at The 51st Annual Design Automation Conference, San Francisco, California, USA, 01 June 2014 - 05 June 2014, http://dx.doi.org/10.1145/2593069.2593159

Ambrose JA; Peddersen J; Parameswaran S; Labios A; Yachide Y, 2014, 'SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs', in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 267 - 273, http://dx.doi.org/10.1109/ASPDAC.2014.6742901

Doan HC; Javaid H; Parameswaran S, 2014, 'Flexible and Scalable Implementation of H.264/AVC Encoder for Multiple Resolutions Using ASIPs', in Preas K (ed.), Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, Institute of Electrical and Electronics Engineers ( IEEE ), Dresden, Germany, pp. 1791 - 1796, presented at DATE, Dresden, Germany, 24 March 2014 - 28 March 2014, http://www.proceedings.com/22046.html

Doan HC; Javaid H; Parameswaran S, 2014, 'Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs', in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, IEEE Conference Publications, pp. 1 - 6, presented at Design Automation and Test in Europe, 24 March 2014 - 28 March 2014, http://dx.doi.org/10.7873/date.2014.366

Nawinne I; Schneider J; Javaid H; Parameswaran S, 2014, 'Hardware-based fast exploration of cache hierarchies in application specific MPSoCs', in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, IEEE Conference Publications, pp. 1 - 6, presented at Design Automation and Test in Europe, 24 March 2014 - 28 March 2014, http://dx.doi.org/10.7873/date.2014.296

Schneider JL; Peddersen J; Parameswaran S, 2014, 'A Scorchingly Fast FPGA-Based Precise L1 LRU Cache Simulator', in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC 2014), IEEE, Singapore, pp. 412 - 417, presented at 2014 19th Asia and South Pacific Design Automation Conference, Singapore, 20 January 2014 - 23 January 2014, http://dx.doi.org/10.1109/ASPDAC.2014.6742926

Aluthwala P; Weste N; Adams A; Lehmann T; Parameswaran S, 2014, 'A simple digital architecture for a harmonic-cancelling sine-wave synthesizer', in Proceedings - IEEE International Symposium on Circuits and Systems, pp. 2113 - 2116, http://dx.doi.org/10.1109/ISCAS.2014.6865584

Bokhari H; Javaid H; Shafique M; Henkel J; Parameswaran S, 2014, 'Darknoc: Designing energyefficient networkonchip with multivt cells for dark silicon', in Proceedings - Design Automation Conference, http://dx.doi.org/10.1145/2593069.2593117

Nawinne I; Schneider J; Javaid H; Parameswaran S, 2014, 'Hardware-based fast exploration of cache hierarchies in application specific MPSoCs', in Proceedings -Design, Automation and Test in Europe, DATE, http://dx.doi.org/10.7873/DATE2014.296

Javaid H; Yachide Y; Shwe SMM; Bokhari H; Parameswaran S, 2014, 'FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs', in Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference, ACM, pp. 33:1 - 33:6, http://dx.doi.org/10.1145/2593069.2593138

Shah SM; Parameswaran S; Sharma V, 2013, 'Previous messages provide the key to achieve shannon capacity in a wiretap channel', in 2013 IEEE International Conference on Communications Workshops, ICC 2013, pp. 697 - 701, http://dx.doi.org/10.1109/ICCW.2013.6649323

Nawinne I; Parameswaran S, 2013, 'A survey on exact cache design space exploration methodologies for application specific SoC memory hierarchies', in 8th IEEE International Conference on Industrial and Information Systems (ICIIS), 2013 - Conference Proceedings, IEEE, IEEE Xplore, pp. 332 - 337, presented at 8th IEEE International Conference on Industrial and Information Systems (ICIIS), 2013, Peradeniya, Sri Lanka, 17 December 2013 - 20 December 2013, http://dx.doi.org/10.1109/ICIInfS.2013.6732005

Min SM; Javaid H; Ignjatovic A; Parameswaran S, 2013, 'A case study on exploration of last-level cache for energy reduction in DDR3 DRAM', in Proceedings - 2013 2nd Mediterranean Conference on Embedded Computing, MECO 2013, pp. 42 - 45, http://dx.doi.org/10.1109/MECO.2013.6601372

Tang X; Parameswaran S; Kishore R; Herath TT, 2013, 'Simulation model of knowledge complexity in new knowledge transfer performance', in 19th Americas Conference on Information Systems, AMCIS 2013 - Hyperconnected World: Anything, Anywhere, Anytime, pp. 2980 - 2989

Bokhari H; Javaid H; Parameswaran S, 2013, 'System-level optimization of on-chip communication using express links for throughput constrained MPSoCs', in 2013 IEEE 11th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia 2013), Montreal, Canada, pp. 68 - 77, presented at ESTIMedia 2013 : The 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, Montreal, Canada, 03 October 2013 - 04 October 2013

Amrouch H; Ebi T; Schneider JL; Parameswaran S; Henkel J, 2013, 'Analyzing the thermal hotspots in FPGA-based embedded systems', in 2013 23rd International Conference on Field Programmable Logic and Applications (FPL 2013), Porto, Portugal, presented at 23rd International Conference on Field Programmable Logic and Applications (FPL), 2013, Porto, Portugal, 02 September 2013 - 04 September 2013, http://dx.doi.org/10.1109/FPL.2013.6645567

Muthukaruppan TS; Javaid H; Mitra T; Parameswaran S, 2013, 'Energy-aware synthesis of application specific MPSoCs', in 2013 IEEE 31st International Conference on Computer Design, ICCD 2013, pp. 62 - 69, http://dx.doi.org/10.1109/ICCD.2013.6657026

Henkel J; Narayanan V; Parameswaran S; Teich J, 2013, 'Run-time adaption for highly-complex multi-core systems', in 2013 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013, http://dx.doi.org/10.1109/CODES-ISSS.2013.6659000

Ambrose JA; Cassisi V; Murphy D; Li T; Jayasinghe D; Parameswaran S, 2013, 'Scalable performance monitoring of application specific multiprocessor Systems-on-Chip', in 2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013 - Conference Proceedings, pp. 315 - 320, http://dx.doi.org/10.1109/ICIInfS.2013.6732002

Li T; Ambrose JA; Parameswaran S, 2012, 'Fine-grained Hardware/Software Methodology for Process Migration in MPSoCs', in Hu A (ed.), International Conference on Computer Aided Design (ICCAD), ACM, New York, USA, pp. 508 - 515, presented at IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, 05 November 2012 - 08 November 2012, http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6386717&contentType=Conference+Publications

Haque S; Ragel RG; Ambrose JA; Radhakrishnan S; Parameswaran S, 2012, 'DIMSim: A Rapid Two-level Cache Simulation Approach for Deadline-based MPSoCs', in The International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)), ACM, New York, USA, pp. 151 - 160, presented at The International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)), Tampere, Finland, 07 October 2012, http://dl.acm.org/citation.cfm?id=2380473

Haque ; Peddersen J; Janapsatya AG; Janapsatya A, 2012, 'SCUD: A Fast Singlepass L1 Cache Simulation Approach for Embedded Processors with Roundrobin Replacement Policy', in 2008 Asia and South Pacific Design Automation Conference, ASP-DAC, ACM, New York, NY, USA, pp. 356 - 361, presented at 2nd International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-oriented Environments. A workshop of the 49th Design Automation Conference (DAC 2012), San Francisco, CA, 03 June 2012 - 07 June 2012, http://dx.doi.org/10.1145/1837274.1837364

Chan JS; Parameswaran S, 2012, 'NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks', in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, San Francisco, CA, presented at 2nd International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-oriented Environments. A workshop of the 49th Design Automation Conference (DAC 2012), San Francisco, CA, 03 June 2012 - 07 June 2012

Ambrose JA; Ignjatovic A; Parameswaran S, 2012, 'CoRaS: A Multiprocessor Key Corruption and Random Round Swapping for Power Analysis Side Channel Attacks: A DES Case Study', in ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems Proceedings, IEEE, South Korea, pp. 253 - 256, presented at IEEE International Symposium on Circuits and Systems, South Korea, 20 May 2012, http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6271818

Parameswaran S; Valecha R; Sharman R; Rao HR; Singh R; Singh G, 2012, 'A prototype of a Patient Safety Knowledge Management System (PSKMS)', in 22nd Workshop on Information Technologies and Systems, WITS 2012, pp. 241

Haque ; Peddersen JMD; Parameswaran S, 2011, 'CIPARSim: Cache Intersection Property Assisted Rapid Single-pass FIFO Cache Simulation Technique', in 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011, IEEE, New York, NY, United States, pp. 126 - 133, presented at 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011, San Jose, CA, United States, 07 November 2011 - 10 November 2011, http://dx.doi.org/10.1109/ICCAD.2011.6105316

Chan JS; Parameswaran S, 2011, 'NOCEE: Energy macro-model extraction methodology for network on chip routers', in ICCAD 2010, San Jose, CA, United States, presented at 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011, San Jose, CA, United States, 07 November 2011 - 10 November 2011

Doan H; Javaid H; Parameswaran S, 2011, 'Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos', in 2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2011, IEEE, Piscataway, United States, pp. 56 - 65, presented at 2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2011, Taipei, Taiwan, 13 October 2011 - 14 October 2011, http://dx.doi.org/10.1109/ESTIMedia.2011.6088526

Kamakoti V; Narayanan V; Sur-Kolay S; Parameswaran S, 2011, 'Welcome message from the symposium chairs', in Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, http://dx.doi.org/10.1109/ISVLSI.2011.4

Javaid H; Shafique M; Parameswaran S; Henkel J, 2011, 'Low-power adaptive pipelined MPSoCs for multimedia: An H.264 video encoder case study', in Proceedings - Design Automation Conference, Institute of Electrical and Electronics Engineers Inc.,, San Diego, CA, United states, pp. 1032 - 1037, presented at 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011, San Diego, CA, United states, 05 June 2011 - 09 June 2011

Shwe SMM; Peddersen JMD; Parameswaran S, 2011, 'Realizing cycle accurate processor memory simulation via interface abstraction', in Proceedings of the IEEE International Conference on VLSI Design 2011, Chennai, India, pp. 141 - 146, presented at 24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems, Chennai, India, 02 January 2011 - 07 January 2011, http://dx.doi.org/10.1109/VLSID.2011.36

Javaid H; Ignjatovic A; Parameswaran S, 2010, 'Fidelity metrics for estimation models', in ICCAD 2010, San Jose, CA, USA, pp. 1 - 8, presented at IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010, San Jose, CA, USA, 07 November 2010 - 11 November 2010, http://dx.doi.org/10.1109/ICCAD.2010.5653959

Javaid H; He X; Ignjatovic A; Parameswaran S, 2010, 'Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications', in International Conference on Hardware/Software CoDesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, pp. 75 - 84, presented at 6th International Conference on Hardware/Software CoDesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, 24 October 2010 - 29 October 2010, http://dx.doi.org/10.1145/1878961.1878978

He X; Peddersen JM; Parameswaran S, 2010, 'LOP: A NOVEL SRAM-BASED ARCHITECTURE FOR LOW POWER AND HIGH THROUGHPUT PACKET CLASSIFICATION', in International Conference on Hardware/Software CoDesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, presented at 6th International Conference on Hardware/Software CoDesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, 24 October 2010 - 29 October 2010

Haque MS; Janapsatya AG; Parameswaran S, 2010, 'SuSeSim: A FAST SIMULATION STRATEGY TO FIND OPTIMAL L1 CACHE CONFIGURATION FOR EMBEDDED SYSTEMS', in International Conference on Hardware/Software CoDesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, presented at 6th International Conference on Hardware/Software CoDesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, 24 October 2010 - 29 October 2010

Shee SL; Erdos A; Parameswaran S, 2010, 'Heterogenous Multiprocessor Implementations for JPEG: A Case Study', in International Conference on Hardware/Software CoDesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, presented at 6th International Conference on Hardware/Software CoDesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, 24 October 2010 - 29 October 2010

Ragel RG; Ambrose JA; Peddersen J; Parameswaran S, 2010, 'RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors', in IFIP AICT 329, Springer, Berlin, Germany, pp. 137 - 144, presented at 7th IFIP Conference on Distributed and Parallel Embedded Systems, Brisbane, Australia, 20 September 2010 - 23 September 2010, http://dx.doi.org/10.1007/978-3-642-15234-4_14

Haque ; Peddersen J; Janapsatya AG; Janapsatya A, 2010, 'DEW: A Fast Level 1 Cache Simulation Approach for Embedded Processors with FIFO Replacement Policy', in Proceedings of the Design, Automation and Test in Europe Conference, European Design and Automation Association, 3001 Leuven, Belgium, Belgium, pp. 496 - 501, presented at Design, Automation and Test in Europe, Dresden, Germany, 08 March 2010 - 12 March 2010, http://portal.acm.org/citation.cfm?id=1870926.1871044

Janapsatya AG; Ignjatovic A; Peddersen J; Parameswaran S, 2010, 'Dueling CLOCK: Adaptive Cache Replacement Policy Based on the CLOCK Algorithm', in Proceedings of the Design, Automation and Test in Europe Conference, European Design and Automation Association, 3001 Leuven, Belgium, Belgium, presented at Design, Automation and Test in Europe, Dresden, Germany, 08 March 2010 - 12 March 2010, http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5456920&tag=1

Javaid H; Janapsatya A; Haque ; Parameswaran S, 2010, 'Rapid Runtime Estimation Methods for Pipelined MPSoCs', in Design, Automation and Test in Europe, European Design and Automation Association, 3001 Leuven, Belgium, Belgium, pp. 363 - 368, presented at Design, Automation and Test in Europe, Dresden, Germany, 08 March 2010 - 12 March 2010, http://portal.acm.org/citation.cfm?id=1870926.1871015

Avnit K; D Silva VV; Sowmya A; Ramesh S, 2010, 'A formal approach to the protocol converter problem', in Proceedings of the Design, Automation and Test in Europe Conference, European Design and Automation Association, 3001 Leuven, Belgium, Belgium, presented at Design, Automation and Test in Europe, Dresden, Germany, 08 March 2010 - 12 March 2010

Henkel J; Parameswaran S, 2009, 'Message from the CASES 2009 Conference Chairs', in Embedded Systems Week 2009 - 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES'09

He X; Peddersen JM; Parameswaran S, 2009, 'LOP_RE: RANGE ENCODING FOR LOW POWER PACKET CLASSIFICATION', in PROCEEDINGS OF IEEELCN 2009, IEEE, Zurich, Switzerland, presented at 34th IEEE Conference on Local Computer networks(IEEE LCN) 2009, Zurich, Switzerland, 20 October 2009 - 23 October 2009

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