ORCID as entered in ROS
https://orcid.org/0000-0003-0435-9080
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Conference Papers
, 2009, 'CUFFS: An Instruction Count Based Architectural framework for Security of MPSOC`s', in proceedings of the Design Automation and Test in Europe, KP Publications, Nice, France, presented at
, 2009, 'Flexible Multi-Mode embedded Floating Point Unit for Field Programmable Gate Arrays', in Proceedings of the 7th ACM SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA`09, Monterey, CA, USA, presented at
, 2009, 'Security and Dependability of Embedded Systems: A Computer Architects' Perspective', in 22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, IEEE COMPUTER SOC, INDIA, New Delhi, pp. 30 - 32, presented at
, 2009, 'A DESIGN FLOW FOR APPLICATION SPECIFIC HETEROGENEOUS PIPELINED MULTIPROCESSOR SYSTEMS', in Proceedings of the 46th Design Automation Conference, The Association for Computing Machinery, New York, NY, USA, presented at
, 2009, 'HitME: Low power hit memory buffer for embedded systems', tokyo, tokyo, http://portal.acm.org/citation.cfm?id=1509633.1509720&coll=GUIDE&dl=ACM&type=series&idx=SERIES480&part=series&WantType=Proceedings&title=ASPDAC
, 2008, 'MCAD: Multiple connection based anomaly detection', in The Eleventh IEEE International Conference on Communication Systems Proceedings, Guangzhou, China, presented at
, 2008, 'MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attacks of the AES algorithm', in International conference on computer aided design, San Jose, California USA, presented at
, 2008, 'LOCS: a low overhead profiler-driven design flow for security of MPSoCs', in CODES + ISS20 08, Atlanta, Georgia USA, presented at
, 2008, 'Synthesis of heterogeneous pipelined multiprocessor systems using ILP: JPEG case study', in CODES + ISS20 08, Atlanta, Georgia USA, presented at
, 2008, 'Rapid application specific floating-point unit generation with bit-alignment', in 45th design automation conference, Anaheim, California, presented at
, 2008, 'SHIELD: a software hardware design methodology for security and reliability of MPSoCs', in 45th design automation conference, Anaheim, California, presented at
, 2008, 'Rapid application specific floating-point unit generation with bit-alignment', in Proceedings of the 45th annual Design Automation Conference, ACM, pp. 62 - 67, presented at
, 2008, 'SHIELD', in Proceedings of the 45th annual Design Automation Conference, ACM, pp. 858 - 861, presented at
, 2008, 'A formal approach to the protocol converter problem', in Proceedings of the conference on Design, automation and test in Europe, ACM, pp. 294 - 299, presented at
, 2008, 'Embedded Systems Week 2008 - Proceedings of the 2008 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES'08: Foreword', in Embedded Systems Week 2008 - Proceedings of the 2008 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES'08
, 2007, 'A smart random code injection to mask power analysis based side channel attacks', in CODES + ISSS 2007: International conference on hardware/software codesign and systems synthesis, Salsburg, Austria, presented at
, 2007, 'Ensuring secure program execution in multiprocessor embedded systems: a case study', in CODES + ISSS 2007: International conference on hardware/software codesign and systems synthesis, Salsburg, Austria, presented at
, 2007, 'Design methodology for pipelined heterogeneous multiprocessor system', in 44th Design automation conference, San Diego, Californa, USA, presented at
, 2007, 'Design methodology for pipelined heterogeneous multiprocessor system', in Proceedings of the 44th annual conference on Design automation - DAC '07, ACM Press, pp. 811 - 811, presented at
, 2007, 'RIJID', in Proceedings of the 44th annual conference on Design automation - DAC '07, ACM Press, pp. 489 - 489, presented at
, 2007, 'RIJID: random code injection to mask power analysis based side channel attacks', in 44th Design automation conference, San Diego, Californa, USA, presented at
, 2007, 'Automatic application specific floating-point unit generation', in Design, automation and test in Europe 2007, Munich, Germany, presented at
, 2007, 'Instruction trace compression for rapid instruction cache simulation', in Design, automation and test in Europe 2007, Munich, Germany, presented at
, 2007, 'Clipper: counter-based low impact processor power estimation at run-time', in 12th Asia and South-Pacific design automation conference, Yokohama, Japan, presented at
, 2007, 'Energy driven application self-adaptation at run-time', in 20th international conference on VLSI design, Bangalore, India, presented at
, 2006, 'Application specific forwarding network and instruction encoding for multi-pipe ASIPs', in CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis, pp. 241 - 246, http://dx.doi.org/10.1145/1176254.1176313
, 2006, 'Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability', in CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis, pp. 100 - 105, http://dx.doi.org/10.1145/1176254.1176280
, 2006, 'Minimising the energy consumption of real-time tasks with precedence constraints on a single processor', in Embedded and ubiquitous computing 2006, Seoul, South Korea, presented at
, 2006, 'IMPRES: integrated monitoring for processor reliability and security', in 43rd Design automation conference 2006, San Francisco, California USA, presented at
, 2006, 'Customization of application specific heterogeneous multi-pipeline processors', in 43rd Design automation conference, Munich, Germany, presented at
, 2006, 'Customization of application specific heterogeneous multi-pipeline processors', in Proceedings of the Design Automation & Test in Europe Conference, IEEE, pp. 6 pp. - 6 pp., presented at
, 2006, 'A novel instruction scratchpad memory optimization method based on concomitance metric', in ASPDAC 2006, Yokohama, Japan, presented at
, 2006, 'A novel instruction scratchpad memory optimization method based on concomitance metric', in Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06, ACM Press, pp. 612 - 612, presented at
, 2006, 'Finding optimal L1 cache configuration for embedded systems', in ASPDAC 2006, Yokohama, Japan, presented at
, 2006, 'Finding optimal L1 cache configuration for embedded systems', in Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06, ACM Press, pp. 796 - 796, presented at
, 2006, 'ADC precision requirement for digital ultra-wideband receivers with sublinear front-ends: A power and performance perspective', in Proceedings of the VLSI Design Conferences, India, presented at
, 2005, 'Micro monitoring for security in application specific instruction-set processors', in International conference on compilers, architectures and synthesis for embedded systems, San Francisco, California USA, presented at
, 2005, 'Novel architecture for loop acceleration: A case study', in international conference on hardware/software codesign, Jersey City, NJ, USA, presented at
, 2005, 'Balancing system level pipelines with stage voltage scaling', in IEEE annual symposium on VLSI, Tampa, Florida, USA, presented at
, 2005, 'The effect of receiver front-end non-linearity on DS-UWB systems operating in the 3 to 4GHz band', in IEEE Wireless communications and networking conference, New Orleans, Louisiana, USA, presented at
, 2005, 'Battery aware instruction generation for embedded processors', in ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, IEEE, PEOPLES R CHINA, Shanghai, pp. 553 - 556, presented at
, 2005, 'Rapid embedded hardware/software system generation', in 18th international conference on VLSI design 2005, Kolkata, India, presented at
, 2004, 'A Quantitative Study and Estimation Models for Extensible Instructions in Embedded Processors', in ICCAD2004 (International Conference on Computer Aided Design), San Jose, California USA, presented at
, 2004, 'Hardware/Software managed scratchpad memory for embedded systems', in ICCAD2004 (International Conference on Computer Aided Design), San Jose, California USA, presented at
, 2004, 'Dual-Pipeline Heterogeneous ASIP Design', in CODES + ISSS 2004, Stockholm, Sweden, presented at
, 2004, 'MINCE: Matching INstructions with Combinational Equivalence for Extensible Processor', in Proceedings Design, Automation and Test in Europe Conference and Exhibition, IEEE, Paris, France, presented at
, 2004, 'NoCGEN: a template based reuse methodology for networks on chip architecture', in 17th International Conference on VLSI Design, Mumbai India, presented at
, 2003, 'A Digital Ultra-Wideband Multiband Transceiver Architecture with Fast Frequency Hopping Capabilities', in 2003 IEEE Conference on Ultra Wideband Systems and Technologies, Reston, Virginia, USA, presented at
, 2003, 'INSIDE: Instruction Selection/Identification & Design Exploration for Extensible Processors', in 18th IEEE International Conference on Data Engineering (ICDE 2002), San Jose, California USA, presented at
, 2003, 'Rapid configuration & instruction selection for an ASIP: A case study', in DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, PROCEEDINGS, IEEE COMPUTER SOC, GERMANY, MUNICH, pp. 802 - 807, presented at
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https://orcid.org/0000-0003-0435-9080