By Professor Sri Parameswaran

Conference Papers

Chong YJ; Parameswaran S, 2008, 'Rapid application specific floating-point unit generation with bit-alignment', in Proceedings of the 45th annual Design Automation Conference, ACM, pp. 62 - 67, presented at DAC '08: The 45th Annual Design Automation Conference 2008, http://dx.doi.org/10.1145/1391469.1391487

Patel K; Parameswaran S, 2008, 'SHIELD', in Proceedings of the 45th annual Design Automation Conference, ACM, pp. 858 - 861, presented at DAC '08: The 45th Annual Design Automation Conference 2008, http://dx.doi.org/10.1145/1391469.1391686

Avnit K; D'Silva V; Sowmya A; Ramesh S; Parameswaran S, 2008, 'A formal approach to the protocol converter problem', in Proceedings of the conference on Design, automation and test in Europe, ACM, pp. 294 - 299, presented at DATE '08: Design, Automation and Test in Europe, http://dx.doi.org/10.1145/1403375.1403447

Altman E; Parameswaran S, 2008, 'Embedded Systems Week 2008 - Proceedings of the 2008 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES'08: Foreword', in Embedded Systems Week 2008 - Proceedings of the 2008 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES'08

Parameswaran S; Ragel RG; Ambrose JA, 2007, 'A smart random code injection to mask power analysis based side channel attacks', in CODES + ISSS 2007: International conference on hardware/software codesign and systems synthesis, Salsburg, Austria, presented at CODES + ISSS 2007: International conference on hardware/software codesign and systems synthesis, Salsburg, Austria, 30 September 2007 - 03 October 2007

Patel K; Parameswaran S; Shee SL, 2007, 'Ensuring secure program execution in multiprocessor embedded systems: a case study', in CODES + ISSS 2007: International conference on hardware/software codesign and systems synthesis, Salsburg, Austria, presented at CODES + ISSS 2007: International conference on hardware/software codesign and systems synthesis, Salsburg, Austria, 30 September 2007 - 03 October 2007

Shee SL; Parameswaran S, 2007, 'Design methodology for pipelined heterogeneous multiprocessor system', in 44th Design automation conference, San Diego, Californa, USA, presented at 44th Design automation conference, San Diego, Californa, USA, 04 June 2007 - 08 June 2007

Shee SL; Parameswaran S, 2007, 'Design methodology for pipelined heterogeneous multiprocessor system', in Proceedings of the 44th annual conference on Design automation - DAC '07, ACM Press, pp. 811 - 811, presented at the 44th annual conference, 04 June 2007 - 08 June 2007, http://dx.doi.org/10.1145/1278480.1278682

Ambrose JA; Ragel RG; Parameswaran S, 2007, 'RIJID', in Proceedings of the 44th annual conference on Design automation - DAC '07, ACM Press, pp. 489 - 489, presented at the 44th annual conference, 04 June 2007 - 08 June 2007, http://dx.doi.org/10.1145/1278480.1278606

Ambrose JA; Ragel RG; Parameswaran S, 2007, 'RIJID: random code injection to mask power analysis based side channel attacks', in 44th Design automation conference, San Diego, Californa, USA, presented at 44th Design automation conference, San Diego, Californa, USA, 04 June 2007 - 08 June 2007

Chong Y; Parameswaran S, 2007, 'Automatic application specific floating-point unit generation', in Design, automation and test in Europe 2007, Munich, Germany, presented at Design, automation and test in Europe 2007, Munich, Germany, 16 April 2007 - 20 April 2007

Janapsatya AG; Ignjatovic A; Parameswaran S; Henkel J, 2007, 'Instruction trace compression for rapid instruction cache simulation', in Design, automation and test in Europe 2007, Munich, Germany, presented at Design, automation and test in Europe 2007, Munich, Germany, 16 April 2007 - 20 April 2007, http://dx.doi.org/10.1109/DATE.2007.364389

Peddersen JM; Parameswaran S, 2007, 'Clipper: counter-based low impact processor power estimation at run-time', in 12th Asia and South-Pacific design automation conference, Yokohama, Japan, presented at 12 Asia and South-Pacific design automation conference, Yokohama, Japan, 23 January 2007 - 26 January 2007

Peddersen JM; Parameswaran S, 2007, 'Energy driven application self-adaptation at run-time', in 20th international conference on VLSI design, Bangalore, India, presented at 20th international conference on VLSI design, Bangalore, India, 06 January 2007 - 10 January 2007

Radhakrishnan S; Guo H; Parameswaran S; Ignjatovic A, 2006, 'Application specific forwarding network and instruction encoding for multi-pipe ASIPs', in CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis, pp. 241 - 246, http://dx.doi.org/10.1145/1176254.1176313

Ragel RG; Parameswaran S, 2006, 'Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability', in CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis, pp. 100 - 105, http://dx.doi.org/10.1145/1176254.1176280

Wu H; Parameswaran S, 2006, 'Minimising the energy consumption of real-time tasks with precedence constraints on a single processor', in Embedded and ubiquitous computing 2006, Seoul, South Korea, presented at Embedded and ubiquitous computing 2006, Seoul, South Korea, 01 August 2006 - 04 August 2006

Parameswaran S; Ragel RG, 2006, 'IMPRES: integrated monitoring for processor reliability and security', in 43rd Design automation conference 2006, San Francisco, California USA, presented at 43rd Design automation conference 2006, San Francisco, California USA, 24 July 2006 - 28 July 2006

Radhakrishnan S; Guo HA; Parameswaran S, 2006, 'Customization of application specific heterogeneous multi-pipeline processors', in 43rd Design automation conference, Munich, Germany, presented at 43rd Design automation conference, Munich, Germany, 06 March 2006 - 10 March 2006

Radhakrishnan S; Hui Guo ; Parameswaran S, 2006, 'Customization of application specific heterogeneous multi-pipeline processors', in Proceedings of the Design Automation & Test in Europe Conference, IEEE, pp. 6 pp. - 6 pp., presented at 2006 Design, Automation and Test in Europe, 06 March 2006 - 10 March 2006, http://dx.doi.org/10.1109/date.2006.244094

Janapsatya AG; Ignjatovic A; Parameswaran S, 2006, 'A novel instruction scratchpad memory optimization method based on concomitance metric', in ASPDAC 2006, Yokohama, Japan, presented at ASPDAC 2006, Yokohama, Japan, 24 January 2006 - 27 January 2006

Janapsatya A; Ignjatović A; Parameswaran S, 2006, 'A novel instruction scratchpad memory optimization method based on concomitance metric', in Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06, ACM Press, pp. 612 - 612, presented at the 2006 conference, 24 January 2006 - 27 January 2006, http://dx.doi.org/10.1145/1118299.1118443

Janapsatya AG; Ignjatovic A; Parameswaran S, 2006, 'Finding optimal L1 cache configuration for embedded systems', in ASPDAC 2006, Yokohama, Japan, presented at ASPDAC 2006, Yokohama, Japan, 24 January 2006 - 27 January 2006

Janapsatya A; Ignjatović A; Parameswaran S, 2006, 'Finding optimal L1 cache configuration for embedded systems', in Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06, ACM Press, pp. 796 - 796, presented at the 2006 conference, 24 January 2006 - 27 January 2006, http://dx.doi.org/10.1145/1118299.1118482

Lu IS; Weste N; Parameswaran S, 2006, 'ADC precision requirement for digital ultra-wideband receivers with sublinear front-ends: A power and performance perspective', in Proceedings of the VLSI Design Conferences, India, presented at 19th Conference on VLSI Design, India, 03 January 2006 - 07 January 2006, http://dx.doi.org/10.1109/VLSID.2006.32

Ragel RG; Parameswaran S; Kia S, 2005, 'Micro monitoring for security in application specific instruction-set processors', in International conference on compilers, architectures and synthesis for embedded systems, San Francisco, California USA, presented at International Conference on Compilers, Architecture, and Synthesis for Embedded Systems 2006, San Francisco, California USA, 24 September 2005 - 27 September 2005

Shee SL; Parameswaran S; Cheung NL, 2005, 'Novel architecture for loop acceleration: A case study', in international conference on hardware/software codesign, Jersey City, NJ, USA, presented at International Conference on Hardware/Software Code Design 2005, Jersey City, NJ, USA, 19 September 2005 - 21 September 2005

Guo HA; Parameswaran S, 2005, 'Balancing system level pipelines with stage voltage scaling', in IEEE annual symposium on VLSI, Tampa, Florida, USA, presented at IEEE annual symposium on VLSI, Tampa, Florida, USA, 11 May 2005 - 12 May 2005

Lu IS; Weste N; Parameswaran S, 2005, 'The effect of receiver front-end non-linearity on DS-UWB systems operating in the 3 to 4GHz band', in IEEE Wireless communications and networking conference, New Orleans, Louisiana, USA, presented at IEEE Wireless Communications and Networking Conference WCNC 2005, New Orleans, Louisiana, USA, 13 March 2005 - 17 March 2005

Cheung N; Parameswaran S; Henkel J, 2005, 'Battery aware instruction generation for embedded processors', in ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, IEEE, PEOPLES R CHINA, Shanghai, pp. 553 - 556, presented at 10th Asia and South Pacific Design Automation Conference, PEOPLES R CHINA, Shanghai, 18 January 2005 - 21 January 2005, http://dx.doi.org/10.1145/1120725.1120960

Peddersen JM; Shee SL; Janapsatya AG; Parameswaran S, 2005, 'Rapid embedded hardware/software system generation', in 18th international conference on VLSI design 2005, Kolkata, India, presented at 18th international conference on VLSI design 2005, Kolkata, India, 03 January 2005 - 07 January 2005

Cheung NL; Parameswaran S; Henkel J, 2004, 'A Quantitative Study and Estimation Models for Extensible Instructions in Embedded Processors', in ICCAD2004 (International Conference on Computer Aided Design), San Jose, California USA, presented at ICCAD2004 (International Conference on Computer Aided Design), San Jose, California USA, 07 November 2004 - 11 November 2004

Janapsatya AG; Parameswaran S; Ignjatovic A, 2004, 'Hardware/Software managed scratchpad memory for embedded systems', in ICCAD2004 (International Conference on Computer Aided Design), San Jose, California USA, presented at ICCAD2004 (International Conference on Computer Aided Design), San Jose, California USA, 07 November 2004 - 11 November 2004

Parameswaran S; Guo HA; Radhakrishnan S, 2004, 'Dual-Pipeline Heterogeneous ASIP Design', in CODES + ISSS 2004, Stockholm, Sweden, presented at CODES + ISSS 2004, Stockholm, Sweden, 08 September 2004 - 10 September 2004

Cheung NL; Parameswaran S; Henkel J; Chan JS, 2004, 'MINCE: Matching INstructions with Combinational Equivalence for Extensible Processor', in Proceedings Design, Automation and Test in Europe Conference and Exhibition, IEEE, Paris, France, presented at Design Automation and Test in Europe (DATE), Paris, France, 16 February 2004 - 20 February 2004

Chan JS; Parameswaran S, 2004, 'NoCGEN: a template based reuse methodology for networks on chip architecture', in 17th International Conference on VLSI Design, Mumbai India, presented at 17th International Conference on VLSI Design, Mumbai India, 05 January 2004 - 09 January 2004

Lu IS; Weste N; Parameswaran S, 2003, 'A Digital Ultra-Wideband Multiband Transceiver Architecture with Fast Frequency Hopping Capabilities', in 2003 IEEE Conference on Ultra Wideband Systems and Technologies, Reston, Virginia, USA, presented at IEEE Conference on Ultra Wideband Systems and Technologies 2003, Reston, Virginia, USA, 16 November 2003 - 19 November 2003

Cheung NL; Parameswaran S; Henkel J, 2003, 'INSIDE: Instruction Selection/Identification & Design Exploration for Extensible Processors', in 18th IEEE International Conference on Data Engineering (ICDE 2002), San Jose, California USA, presented at 18th IEEE International Conference on Data Engineering (ICDE 2002), San Jose, California USA, 09 November 2003 - 13 November 2003

Cheung N; Henkel J; Parameswaran S, 2003, 'Rapid configuration & instruction selection for an ASIP: A case study', in DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, PROCEEDINGS, IEEE COMPUTER SOC, GERMANY, MUNICH, pp. 802 - 807, presented at Design, Automation and Test in Europe Conference and Exhibition (DATE 03), GERMANY, MUNICH, 03 March 2003 - 07 March 2003, https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000182683800128&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=891bb5ab6ba270e68a29b250adbe88d1

Parameswaran S; Henkel J; Lekastas H, 2003, 'Multi-parametric improvements for embedded systems using code-placement and address bus coding', in Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC, ACM Press, pp. 15 - 15, presented at the 2003 conference, 21 January 2003 - 24 January 2003, http://dx.doi.org/10.1145/1119772.1119776

Parameswaran S; Henkel J; Lekastas H, 2003, 'Multi-parametric improvements for embedded systems using code-placement and address bus coding', in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 15 - 21, http://dx.doi.org/10.1109/ASPDAC.2003.1194987

Cheung N; Henkel J; Parameswaran S, 2003, 'Rapid Configuration & Instruction Selection for an ASIP: A Case Study', Institute of Electrical and Electronics Engineers (IEEE), pp. 1 - 6, presented at 2003 Design, Automation and Test in Europe Conference and Exhibition, http://dx.doi.org/10.1109/date.2003.1253705

Parameswaran S, 2002, 'SWASAD: an ASIC design for high speed DNA sequence matching', in ASP-DAC/VLSI-Design-2002.-7th-Asia-and-South-Pacific-Design-Automation-Conference-and-15h-International-Conference-on-VLSI-Design. 2002, Bangalore, India, presented at ASP-DAC/VLSI-Design-2002.-7th-Asia-and-South-Pacific-Design-Automation-Conference-and-15h-International-Conference-on-VLSI-Design. 2002, Bangalore, India, 07 January 2002 - 11 January 2002

Parameswaran S, 2001, 'Code placement in hardware software Co synthesis to improve performance and reduce cost', in Proceedings -Design, Automation and Test in Europe, DATE, pp. 626 - 632, http://dx.doi.org/10.1109/DATE.2001.915089

Rae A; Parameswaran S, 2000, 'Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation', in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 147 - 152, http://dx.doi.org/10.1145/368434.368594

Boros VE; Rakic AD; Parameswaran S, 2000, 'High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system', in Proceedings - Design Automation Conference, pp. 221 - 226, http://dx.doi.org/10.1145/337292.337395

Rae A; Parameswaran S, 1998, 'Application-specific heterogeneous multiprocessor synthesis using differential-evolution', in Proceedings of the International Symposium on System Synthesis, pp. 83 - 88, http://dx.doi.org/10.1109/isss.1998.730602

Parameswaran S; Guo H, 1997, 'Partitioning of system level pipelines', in Proceedings of the Australian Microelectronics Conference, pp. 233 - 238

Parameswaran S; Guo H, 1997, 'Power reduction in pipelines', in Proceedings of the Australian Microelectronics Conference, pp. 239 - 244

Guo H; Parameswaran S, 1997, 'Unfolding loops with interdetermine count in system level pipelines', in Proceedings of the Australian Microelectronics Conference, pp. 82 - 87

Back to profile page