Select Publications
Journal articles
2012, 'Differential Power Analysis in AES: A Crypto Anatomy', IJEI: International Journal of Engineering and Industries, 2, pp. 118 - 130, http://www.aicit.org/ijei/global/paper_detail.html?jname=IJEI&q=46
,2012, 'Randomized Instruction Injection to Counter Power Analysis Attacks', ACM Transactions on Embedded Computing Systems (TECS), 11, pp. 28, http://dl.acm.org/citation.cfm?id=2345782
,2011, 'A hybrid hardware-software technique to improve reliability in embedded processors', ACM Transactions on Embedded Computing Systems (TECS), 10, pp. Article number: 36, http://dx.doi.org/10.1145/1952522.1952529
,2011, 'Architectural frameworks for security and reliability of MPSoCs', IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 19, pp. 1641 - 1654, http://dx.doi.org/10.1109/TVLSI.2010.2053856
,2011, 'Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks', IET Computers and Digital Techniques, 5, pp. 1 - 15, http://dx.doi.org/10.1049/iet-cdt.2009.0097
,2010, 'Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications', 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2010, pp. 75 - 84
,2010, 'CASES 2009 guest editor's introduction', Design Automation for Embedded Systems, 14, pp. 285 - 286, http://dx.doi.org/10.1007/s10617-010-9060-4
,2010, 'Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29, pp. 1777 - 1789, http://dx.doi.org/10.1109/TCAD.2010.2061353
,2009, 'Custom floating-point unit generation for embedded systems', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28, pp. 638 - 650
,2009, 'Custom Floating-Point Unit Generation for Embedded Systems', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28, pp. 638 - 650
,2009, 'HMP-ASIP`s: heterogeneous multi-pipeline application-specific instruction-set processors', IET Computers and Digital Techniques, 3, pp. 94 - 108
,2009, 'Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis', ACM Transactions on Design Automation of Electronic Systems, 14
,2008, 'Architectural exploration of heterogeneous multiprocessor systems for JPEG', International Journal of Parallel Programming, 36, pp. 140 - 162, http://dx.doi.org/10.1007/s10766-007-0040-7
,2008, 'Embedded systems security - an overview', Design Automation for Embedded Systems, 12, pp. 173 - 183
,2008, 'Energy driven application self-adaptation at run-time', Journal of Computers (JCP), 3, pp. 14 - 24, http://dx.doi.org/10.4304/jcp.3.3.14-24
,2008, 'Guest editorial for special issue on embedded system security', Design Automation for Embedded Systems, 12, pp. 171 - 172
,2008, 'Low-impact processor for dynamic runtime power management', IEEE Design and Test of Computers, 25, pp. 52 - 62, http://dx.doi.org/10.1109/MDT.2008.23
,2007, 'Instruction matching and modeling', Customizable Embedded Processors, pp. 257 - 280, http://dx.doi.org/10.1016/B978-012369526-0/50012-7
,2007, 'A power-efficient 5.6-GHz process-compensated CMOS frequency divider', IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 54, pp. 323 - 327, http://dx.doi.org/10.1109/TCSII.2006.889741
,2007, 'Low-Impact processor for dynamic runtime power management', IEEE Design & Test of Computers, 24, pp. x4 - x4, http://dx.doi.org/10.1109/mdt.2007.4343581
,2006, 'Exploiting statistical information for implementation of instruction scratchpad memory in embedded systems', IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 14, pp. 816 - 829
,2005, 'Instruction code mapping for performance increase and energy reduction in embedded computer systems', IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 13, pp. 498 - 502
,2004, 'Foreword', Sensorium - A neuroscience journal for Australasian clinicians, Issue 5, pp. 1 - 1
,2004, 'REMcode: relocating embedded code for improving system efficiency', IEE Proceedings-Computers and Digital Techniques, 151, pp. 457 - 465
,2001, 'Synthesising application-specific heterogeneous multiprocessors using differential evolution', IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E84A, pp. 3125 - 3131, https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000172877000020&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=891bb5ab6ba270e68a29b250adbe88d1
,2001, 'Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation', IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E84A, pp. 2296 - 2302, https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000171700800027&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=891bb5ab6ba270e68a29b250adbe88d1
,2001, 'I-CoPES: Fast instruction code placement for embedded systems to improve performance and energy efficiency', IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, pp. 635 - 641, http://dx.doi.org/10.1109/ICCAD.2001.968728
,2001, 'Synthesising application-specific heterogeneous multiprocessors using differential evolution', IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E84-A, pp. 3125 - 3131
,2001, 'Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation', IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E84-A, pp. 2296 - 2302
,2000, 'Profiling in the ASP codesign environment', Journal of Systems Architecture, 46, pp. 1263 - 1274, http://dx.doi.org/10.1016/S1383-7621(00)00016-3
,1999, 'Self-checking synchronous controller design', IEE Proceedings: Computers and Digital Techniques, 146, pp. 9 - 12, http://dx.doi.org/10.1049/ip-cdt:19990243
,1998, 'HW-SW co-synthesis: The present and the future', Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 19 - 22
,1998, 'Power reduction in pipelines', Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 545 - 550
,1998, 'Designs for self checking flip-flops', IEE Proceedings: Computers and Digital Techniques, 145, pp. 81 - 88, http://dx.doi.org/10.1049/ip-cdt:19981907
,1995, 'Reclocking controllers for minimum execution time', IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E78-A, pp. 1715 - 1721
,1995, 'Reclocking controllers for minimum execution time', IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E78A, pp. 1715 - 1721, https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:A1995TM34400016&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=891bb5ab6ba270e68a29b250adbe88d1
,Conference Papers
2024, 'Sensors for Remote Power Attacks: New Developments and Challenges', in 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), IEEE, presented at 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 22 January 2024 - 25 January 2024, http://dx.doi.org/10.1109/asp-dac58780.2024.10473890
,2023, 'FPGA Based Countermeasures against Side Channel Attacks on Block Ciphers', in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 365 - 371, http://dx.doi.org/10.1145/3566097.3568353
,2023, 'Invited: Algorithms and Architectures for Accelerating Long Read Sequence Analysis', in Proceedings - Design Automation Conference, http://dx.doi.org/10.1109/DAC56929.2023.10247772
,2022, 'FaSe: Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks', in Proceedings - Design Automation Conference, pp. 541 - 546, http://dx.doi.org/10.1145/3489517.3530491
,2022, 'HWST128: Complete Memory Safety Accelerator on RISC-V with Metadata Compression', in Proceedings - Design Automation Conference, pp. 709 - 714, http://dx.doi.org/10.1145/3489517.3530548
,2021, 'SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V', in Proceedings - Design Automation Conference, pp. 289 - 294, http://dx.doi.org/10.1109/DAC18074.2021.9586293
,2021, 'Approximate Computing for ML: State-of-the-art, Challenges and Visions', in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 189 - 196, http://dx.doi.org/10.1145/3394885.3431632
,2020, 'Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping', in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, http://dx.doi.org/10.1145/3400302.3415651
,2020, 'FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications', in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 3577 - 3588, http://dx.doi.org/10.1109/TCAD.2020.3012211
,2020, 'LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs', in Proceedings - 30th International Conference on Field-Programmable Logic and Applications, FPL 2020, pp. 162 - 168, http://dx.doi.org/10.1109/FPL50879.2020.00036
,2020, 'REALM: Reduced-Error Approximate Log-based Integer Multiplier', in Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020, pp. 1366 - 1371, http://dx.doi.org/10.23919/DATE48585.2020.9116315
,2020, 'WEID: Worst-case Error Improvement in Approximate Dividers', in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Institute of Electrical and Electronics Engineers (IEEE), pp. 593 - 598, presented at 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 13 January 2020 - 16 January 2020, http://dx.doi.org/10.1109/asp-dac47756.2020.9045504
,2020, 'A sub-range error characterization based selection methodology for approximate arithmetic units', in Proceedings - 33rd International Conference on VLSI Design, VLSID 2020 - Held concurrently with 19th International Conference on Embedded Systems, pp. 84 - 89, http://dx.doi.org/10.1109/VLSID49098.2020.00032
,2019, 'SCRIP: Secure random clock execution on soft processor systems to mitigate power-based side channel attacks', in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, http://dx.doi.org/10.1109/ICCAD45719.2019.8942112
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