By Professor Sri Parameswaran

Conference Papers

Parkinson MF; Taylor PM; Parameswaran S, 1994, 'C to VHDL converter in a codesign environment', in Spring 1994 Conference - Proceedings VHDL International Users Forum, VIUF 1994, pp. 100 - 109, http://dx.doi.org/10.1109/VIUF.1994.323960

Cheung N; Parameswarant S; Henkel J, 'Battery aware instruction generation for embedded processors', in Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005., IEEE, presented at ASP-DAC 2005. Asia and South Pacific Design Automation Conference 2005, http://dx.doi.org/10.1109/aspdac.2005.1466225

Parkinson MF; Parameswaran S, 'Profiling in the ASP codesign environment', in Proceedings of the Eighth International Symposium on System Synthesis, IEEE Comput. Soc. Press, presented at Eighth International Symposium on System Synthesis, http://dx.doi.org/10.1109/isss.1995.520624

Chandra R; Henkel J; Panda PR; Parameswaran S; Ramachandran L, 'Specification and design of multi-million gate SOCs', in 16th International Conference on VLSI Design, 2003. Proceedings., IEEE Comput. Soc, presented at 16th International Conference on VLSI Design. Concurrently with the 2nd International Conference on Embedded Systems Design, http://dx.doi.org/10.1109/icvd.2003.1183107

Rae A; Parameswaran S, 'Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation', in Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106), IEEE, presented at ASP-DAC2000: Asia and South Pacific Design Automation Conference 2000, http://dx.doi.org/10.1109/aspdac.2000.835086

Conference Posters

Shwe S; Batra K; Yachide Y; Peddersen JM; Parameswaran S, 2015, 'RAPITIMATE: Rapid Performance Estimation of Pipelined Processing Systems Containing Shared Memory', presented at Design Automation Conference (DAC), 07 June 2015 - 11 June 2015

Ambrose JA; Peddersen JM; Yachide Y; Batra K; Parameswaran S, 2015, 'Sequential C-code to Distributed Pipelined Heterogeneous MPSoC Synthesis for Streaming Applications', New York, NY, pp. 216 - 223, presented at Design Automation Conference (DAC), New York, NY, 07 June 2015 - 11 June 2015

Theses / Dissertations

Parameswaran S, 1991, SPOT : A computer aided digital design system, http://dx.doi.org/10.14264/uql.2015.616

Preprints

Samarakoon H; Liyanage K; Ferguson J; Parameswaran S; Gamaarachchi H; Deveson I, 2024, Interactive visualisation of raw nanopore signal data with Squigualiser, , http://dx.doi.org/10.1101/2024.02.19.581111

Liyanage K; Samarakoon H; Parameswaran S; Gamaarachchi H, 2023, minimap2-fpga: Integrating hardware-accelerated chaining for efficient end-to-end long-read sequence mapping, , http://dx.doi.org/10.1101/2023.05.30.542681

Shih PJ; Saadat H; Parameswaran S; Gamaarachchi H, 2022, Efficient Real-Time Selective Genome Sequencing on Resource-Constrained Devices, , http://arxiv.org/abs/2211.07340v1

Gong J; Saadat H; Gamaarachchi H; Javaid H; Hu XS; Parameswaran S, 2022, ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference, , http://dx.doi.org/10.48550/arxiv.2209.04161

Samarakoon H; Ferguson J; Jenner S; Amos T; Parameswaran S; Gamaarachchi H; Deveson I, 2022, Flexible and efficient handling of nanopore sequencing signal data with slow5tools, , http://dx.doi.org/10.1101/2022.06.19.496732

Bayat A; Gamaarachchi H; Deshpande N; Wilkins M; Parameswaran S, 2020, Methods for De-novo Genome Assembly, , http://dx.doi.org/10.20944/preprints202006.0324.v1

Ragel RG; Ambrose JA; Parameswaran S, 2015, SecureD: A Secure Dual Core Embedded Processor, , http://dx.doi.org/10.48550/arxiv.1511.01946

Haque MS; Peddersen J; Parameswaran S, 2015, CIPARSim: Cache Intersection Property Assisted Rapid Single-pass FIFO Cache Simulation Technique, , http://dx.doi.org/10.48550/arxiv.1506.03186

Haque MS; Peddersen J; Janapsatya A; Parameswaran S, 2015, DEW: A Fast Level 1 Cache Simulation Approach for Embedded Processors with FIFO Replacement Policy, , http://dx.doi.org/10.48550/arxiv.1506.03181

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