By Professor Sri Parameswaran

Books

Javaid H; Parameswaran S, 2013, Pipelined Multiprocessor System-on-Chip for Multimedia, Springer

Ambrose JA; Ignjatovic A; Parameswaran S, 2010, Power Analysis Side Channel Attacks: The Processor Design-level Context, Original, VDM Verlag Dr. Müller, Germany, http://www.amazon.com/Power-Analysis-Side-Channel-Attacks/dp/3836485087

Guo HA; Parameswaran S; Radhakrishnan S, 2008, Heterogeneous multi-pipeline ASIP, Original, VDM Verlag, Germany

Henkel J; Parameswaran S, 2007, Designing embedded processors: A low power perspective, http://dx.doi.org/10.1007/978-1-4020-5869-1

Book Chapters

Jayasinghe D; Parameswaran S, 2024, 'SRISC: Open Source Soft Processor Side Channel Analysis Attack Framework Using RISC-V', in , pp. 112 - 124, http://dx.doi.org/10.1007/978-3-031-51135-6_10

Lehmann T; Aluthwala P; Parameswaran S, 2019, 'Digitally enhanced digital-to-analogue converters', in Digitally Enhanced Mixed Signal Systems, pp. 227 - 254

Bokhari H; Parameswaran S, 2017, 'Network-on-chip design', in Handbook of Hardware/Software Codesign, pp. 461 - 489, http://dx.doi.org/10.1007/978-94-017-7267-9_16

Bokhari H; Shafique M; Henkel J; Parameswaran S, 2017, 'Adroit use of dark silicon for power, performance and reliability optimisation of NoCs', in Rahmani A; Liljeberg P; Hemani A; Jantsch A; Tenhunen H (ed.), The Dark Side of Silicon: Energy Efficient Computing in the Dark Silicon Era, Springer, pp. 291 - 325, http://dx.doi.org/10.1007/978-3-319-31596-6_11

Cetin E; Diessel O; Li T; Ambrose J; Fisk T; Parameswaran S; Dempster A, 2016, 'Overview and Investigation of SEU Detection and Recovery Approaches for FPGA-Based Heterogeneous Systems', in FPGAs and Parallel Architectures for Aerospace Applications Soft Errors and Fault-Tolerant Design, Springer, pp. 33 - 46, http://dx.doi.org/10.1007/978-3-319-14352-1_3

Bokhari H; Parameswaran S, 2016, 'Network-on-Chip Design', in Handbook of Hardware/Software Codesign, Springer Netherlands, pp. 1 - 29, http://dx.doi.org/10.1007/978-94-017-7358-4_16-1

Henkel J; Parameswaran S; Cheung N, 2007, 'Application-specific embedded processors', in Designing Embedded Processors: A Low Power Perspective, pp. 3 - 23, http://dx.doi.org/10.1007/978-1-4020-5869-1_1

Henkel J; Parameswaran S, 2007, 'Foreword: Embedded processors -What is next?', in Designing Embedded Processors: A Low Power Perspective, http://dx.doi.org/10.1007/978-1-4020-5869-1

Parameswaran S; Henkel J; Cheung N, 2007, 'Chapter 11 Instruction Matching and Modeling', in Customizable Embedded Processors, Elsevier, pp. 257 - 280, http://dx.doi.org/10.1016/b978-012369526-0/50012-7

Cheung NL; Henkel J; Parameswaran S, 2003, 'Rapid Configuration & Instruction Selection for an ASIP:a Case Study', in Jerraya A; Yoo S; Verkest D; Wehn N (ed.), Embedded Software for, Kluwer Academic Publishers, Boston, USA, pp. 403 - 417

Journal articles

Jayasinghe D; Udugama B; Parameswaran S, 2023, '1LUTSensor: Detecting FPGA Voltage Fluctuations using LookUp Tables', IACR Transactions on Cryptographic Hardware and Embedded Systems, 2024, pp. 51 - 86, http://dx.doi.org/10.46586/tches.v2024.i1.51-86

Liyanage K; Samarakoon H; Parameswaran S; Gamaarachchi H, 2023, 'Efficient end-to-end long-read sequence mapping using minimap2-fpga integrated with hardware accelerated chaining', Scientific Reports, 13, http://dx.doi.org/10.1038/s41598-023-47354-8

Samarakoon H; Ferguson JM; Jenner SP; Amos TG; Parameswaran S; Gamaarachchi H; Deveson IW, 2023, 'Flexible and efficient handling of nanopore sequencing signal data with slow5tools', Genome Biology, 24, http://dx.doi.org/10.1186/s13059-023-02910-3

Gong J; Saadat H; Gamaarachchi H; Javaid H; Hu XS; Parameswaran S, 2023, 'ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 42, pp. 3505 - 3518, http://dx.doi.org/10.1109/TCAD.2023.3253045

Liyanage K; Gamaarachchi H; Ragel R; Parameswaran S, 2023, 'Cross Layer Design Using HW/SW Co-Design and HLS to Accelerate Chaining in Genomic Analysis', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 42, pp. 2924 - 2937, http://dx.doi.org/10.1109/TCAD.2023.3236559

Bosio A; Dolecek L; Kourfali A; Parameswaran S; Savino A, 2023, 'Special Issue: "Approximation at the Edge"', ACM Transactions on Embedded Computing Systems, 22, pp. 1 - 4, http://dx.doi.org/10.1145/3605757

Shih PJ; Saadat H; Parameswaran S; Gamaarachchi H, 2023, 'Efficient real-time selective genome sequencing on resource-constrained devices', GigaScience, 12, http://dx.doi.org/10.1093/gigascience/giad046

Udugama B; Jayasinghe D; Saadat H; Ignjatovic A; Parameswaran S, 2022, 'A Power to Pulse Width Modulation Sensor for Remote Power Analysis Attacks', IACR Transactions on Cryptographic Hardware and Embedded Systems, 2022, pp. 589 - 613, http://dx.doi.org/10.46586/tches.v2022.i4.589-613

Gamaarachchi H; Samarakoon H; Jenner SP; Ferguson JM; Amos TG; Hammond JM; Saadat H; Smith MA; Parameswaran S; Deveson IW, 2022, 'Fast nanopore sequencing data analysis with SLOW5', Nature Biotechnology, 40, pp. 1026 - 1029, http://dx.doi.org/10.1038/s41587-021-01147-4

Hussain S; Guo H; Li T; Saadat H; Parameswaran S, 2021, 'COPS: A complete oblivious processing system', Microprocessors and Microsystems, 85, http://dx.doi.org/10.1016/j.micpro.2021.104295

Jayasinghe D; Ignjatovic A; Ragel R; Ambrose JA; Parameswaran S, 2021, 'QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks', ACM Transactions on Design Automation of Electronic Systems, 26, http://dx.doi.org/10.1145/3443706

Jayasinghe D; Ignjatovic A; Parameswaran S, 2021, 'UCloD: Small Clock Delays to Mitigate Remote Power Analysis Attacks', IEEE Access, 9, pp. 108411 - 108425, http://dx.doi.org/10.1109/ACCESS.2021.3100618

Udugama B; Jayasinghe D; Saadat H; Ignjatovic A; Parameswaran S, 2021, 'VITI: A Tiny Self-Calibrating Sensor for Power-Variation Measurement in FPGAs', IACR Transactions on Cryptographic Hardware and Embedded Systems, 2022, pp. 657 - 678, http://dx.doi.org/10.46586/tches.v2022.i1.657-678

Gamaarachchi H; Samarakoon H; Jenner S; Ferguson J; Amos T; Hammond J; Saadat H; Smith M; Parameswaran S; Deveson I, 2021, 'SLOW5: a new file format enables massive acceleration of nanopore sequencing data analysis', , http://dx.doi.org/10.1101/2021.06.29.450255

Gamaarachchi H; Samarakoon H; Jenner S; Ferguson J; Amos T; Hammond J; Saadat H; Smith M; Parameswaran S; Deveson I, 2021, 'SLOW5: a new file format enables massive acceleration of nanopore sequencing data analysis', , http://dx.doi.org/10.21203/rs.3.rs-668517/v1

Gamaarachchi H; Lam CW; Jayatilaka G; Samarakoon H; Simpson JT; Smith MA; Parameswaran S, 2020, 'GPU accelerated adaptive banded event alignment for rapid comparative nanopore signal analysis', BMC Bioinformatics, 21, http://dx.doi.org/10.1186/s12859-020-03697-x

Gamaarachchi H; Bayat A; Gaeta B; Parameswaran S, 2020, 'Cache Friendly Optimisation of de Bruijn Graph Based Local Re-Assembly in Variant Calling', IEEE/ACM Transactions on Computational Biology and Bioinformatics, 17, pp. 1125 - 1133, http://dx.doi.org/10.1109/TCBB.2018.2881975

Bayat A; Deshpande NP; Wilkins MR; Parameswaran S, 2020, 'Fast Short Read De-Novo Assembly Using Overlap-Layout-Consensus Approach', IEEE/ACM Transactions on Computational Biology and Bioinformatics, 17, pp. 334 - 338, http://dx.doi.org/10.1109/TCBB.2018.2875479

Malekpour A; Ragel R; Tuo LI; Javaid H; Ignjatovic A; Parameswaran S, 2020, 'Hardware Trojan mitigation in pipelined MPSoCs', ACM Transactions on Design Automation of Electronic Systems, 25, http://dx.doi.org/10.1145/3365578

Gamaarachchi H; Parameswaran S; Smith MA, 2019, 'Featherweight long read alignment using partitioned reference indexes', Scientific Reports, 9, pp. 4318, http://dx.doi.org/10.1038/s41598-019-40739-8

Gamaarachchi H; Lam CW; Jayatilaka G; Samarakoon H; Simpson J; Smith M; Parameswaran S, 2019, 'GPU Accelerated Adaptive Banded Event Alignment for Rapid Comparative Nanopore Signal Analysis', bioRxiv, http://dx.doi.org/10.1101/756122

Bayat A; Gaëta B; Ignjatovic A; Parameswaran S, 2019, 'Pairwise alignment of nucleotide sequences using maximal exact matches', BMC Bioinformatics, 20, pp. 261, http://dx.doi.org/10.1186/s12859-019-2827-0

Saadat H; Bokhari H; Parameswaran S, 2018, 'Minimally biased multipliers for approximate integer and floating-point multiplication', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37, pp. 2623 - 2635, http://dx.doi.org/10.1109/TCAD.2018.2857262

Gamaarachchi H; Parameswaran S; Smith M, 2018, 'Featherweight long read alignment using partitioned reference indexes', BIORXIV, http://dx.doi.org/10.1101/386847

Parameswaran S; Iris Bahar R; Pan DZ, 2018, 'Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD)', IEEE Design and Test, 35, pp. 101 - 102, http://dx.doi.org/10.1109/MDAT.2018.2799991

Li T; Shafique M; Ambrose JA; Henkel J; Parameswaran S, 2017, 'Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors', IEEE Transactions on Computers, 66, pp. 647 - 660, http://dx.doi.org/10.1109/TC.2016.2606378

Aluthwala PD; Weste N; Adams A; Lehmann T; Parameswaran S, 2017, 'Partial dynamic element matching technique for digital-to-analog converters used for digital harmonic-cancelling sine-wave synthesis', IEEE Transactions on Circuits and Systems I: Regular Papers, 64, pp. 296 - 309, http://dx.doi.org/10.1109/TCSI.2016.2613938

Liu T; Guo H; Parameswaran S; Hu SX, 2017, 'iCETD: An improved tag generation design for memory data authentication in embedded processor systems', Integration, the VLSI Journal, 56, pp. 96 - 104, http://dx.doi.org/10.1016/j.vlsi.2016.10.006

Bayat A; Gaëta B; Ignjatovic A; Parameswaran S, 2017, 'Improved VCF normalization for accurate VCF comparison.', Bioinformatics, 33, pp. 964 - 970, http://dx.doi.org/10.1093/bioinformatics/btw748

Li T; Ambrose JA; Ragel R; Parameswaran S, 2016, 'Processor design for soft errors: Challenges and state of the art', ACM Computing Surveys, 49, http://dx.doi.org/10.1145/2996357

Nawinne I; Javaid H; Ragel R; Parameswaran S, 2016, 'Switchable cache: Utilising dark silicon for application specific cache optimisations', IET Computers and Digital Techniques, 10, pp. 157 - 164, http://dx.doi.org/10.1049/iet-cdt.2015.0114

Parameswaran S, 2016, 'Editorial Introduction of New Editor-in-Chief and Associate Editors', IEEE Embedded Systems Letters, 8, pp. 1, http://dx.doi.org/10.1109/LES.2016.2532418

Nawinne I; Javaid H; Ragel R; Radhakrishnan S; Parameswaran S, 2015, 'Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34, pp. 1991 - 2003, http://dx.doi.org/10.1109/TCAD.2015.2445736

Ragel RG; Ambrose JA; Parameswaran S, 2015, 'SecureD: A Secure Dual Core Embedded Processor', SecureD: A Secure Dual Core Embedded Processor, http://arxiv.org/abs/1511.01946v1

Javaid H; Shafique M; Henkel J; Parameswaran S, 2014, 'Energy-efficient adaptive pipelined MPSoCs for multimedia applications', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33, pp. 663 - 676, http://dx.doi.org/10.1109/TCAD.2014.2298196

Javaid H; Ignjatovic A; Parameswaran S, 2014, 'Performance estimation of pipelined multiprocessor system-on-chips (MPSoCs)', IEEE Transactions on Parallel and Distributed Systems, 25, pp. 2159 - 2168, http://dx.doi.org/10.1109/TPDS.2013.268

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